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El. knyga: 3D IC Stacking Technology

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  • Formatas: 544 pages
  • Išleidimo metai: 14-Oct-2011
  • Leidėjas: McGraw-Hill Professional
  • Kalba: eng
  • ISBN-13: 9780071741965
Kitos knygos pagal šią temą:
3D IC Stacking TechnologyDidesnis paveikslėlis
  • Formatas: 544 pages
  • Išleidimo metai: 14-Oct-2011
  • Leidėjas: McGraw-Hill Professional
  • Kalba: eng
  • ISBN-13: 9780071741965
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The latest advances in three-dimensional integrated circuit stacking technology

3D IC Stacking Technology is a comprehensive resource on three-dimensional stacking technology, including scientific theory, processing methods, applications, and an overview of the industry's technological future. The book is targeted to semiconductor engineers and portable device designers.

The quality and functional capabilities of nearly all of today’s electronic devices and the production lines that produce them are dependent on key internal semiconductor components—ICs. Lithography and packaging integration are the determining factors in keeping pace with the electronics industry’s quest to have more and more transistors on chip product by shrinking ICs and other related products, or by stacking the multiple chips into one chip device. This in-depth volume covers these cutting-edge technologies.

3D IC Stacking Technology

  • Focuses on industrial applications
  • Includes detailed fabrication processes
  • Covers a separate fabrication step in each chapter, written by an industry expert
  • Provides a one-stop knowledge resource for 3D IC technology
  • Discusses future applications and device design potentials

Comprehensive coverage:
Design challenges; Process sequence integration; TSV etch; Chemical vapor; Barrier/ seed deposition; ECD fill; Chemical mechanical polishing; Wafer thinning; Temporary and permanent bonding; Cost of ownership

Contributors xiii
Foreword xv
Preface xvii
1 Introduction to High-Density Through Silicon Stacking Technology
1(26)
Matthew Nowak
1.1 Background
1(4)
1.2 3D Integrated Circuit Technologies
5(4)
1.2.1 3D IC Types
5(3)
1.2.2 Via-Middle Through Silicon Stacking
8(1)
1.3 TSS Drivers and Product Architectures
9(8)
1.3.1 Overall Drivers
9(1)
1.3.2 Examples of Architectural Uniqueness from Through Silicon Stacking
10(7)
1.3.3 Software Simplification Enabled by TSS
17(1)
1.4 Markets for TSS
17(1)
1.5 TSS Supply Chain Options
18(2)
1.6 Challenges for Through Silicon Stacking
20(3)
1.6.1 Manufacturing Cost
20(1)
1.6.2 Design Tools, Flow, Kits
21(1)
1.6.3 Design for Test and Manufacturing Test
21(1)
1.6.4 Thermal Hotspots, Mechanical Stress, and Power Delivery
22(1)
1.6.5 Fabrication Processes, Materials, and Structures
22(1)
1.6.6 Technology Adoption
22(1)
1.7 Concluding Remarks
23(1)
References
23(4)
2 A Practical Design Eco-System for Heterogeneous 3D IC Products
27(50)
Riko Radojcic
2.1 Requirements for 3D Design Eco-System
29(7)
2.1.1 2D Design Experiences
30(1)
2.1.2 Causes for Incremental Design Specification Instability in 3D
31(2)
2.1.3 Causes for Incremental Process Constraint Instability in 3D
33(2)
2.1.4 3D Design Eco-System
35(1)
2.2 PathFinding
36(10)
2.2.1 PathFinding Objectives
36(3)
2.2.2 Ideal PathFinding Flow
39(3)
2.2.3 PathFinding versus Design-Authoring Requirements
42(2)
2.2.4 3D PathFinding and Trade-Off Discussion
44(2)
2.3 TechTuning
46(17)
2.3.1 TechTuning Objectives
46(3)
2.3.2 TechTuning Implementation
49(12)
2.3.3 TechTuning Infrastructure
61(2)
2.4 Design Authoring
63(10)
2.4.1 Design Enablement
65(1)
2.4.2 Synthesis and Simulation
66(1)
2.4.3 Physical Design, Extraction, and Verification
66(3)
2.4.4 Utility Insertion
69(3)
2.4.5 Timing and Power Analyses
72(1)
2.5 Summary and Conclusions
73(1)
References
73(4)
3 Design Automation and TCAD Tool Solutions for Through Silicon Via-Based 3D IC Stack
77(36)
Jamil Kawa
Xiaopeng Xu
3.1 Introduction
77(1)
3.2 Planning: 3D System Architecture
78(2)
3.2.1 PathFinding
78(1)
3.2.2 Gross Thermal Analysis
79(1)
3.2.3 Board-Package-IC Co-Design
79(1)
3.3 Implementation
80(7)
3.3.1 Partitioning
80(1)
3.3.2 Floor Planning and Place and Route
80(2)
3.3.3 Clock and Power Networks
82(3)
3.3.4 Testability
85(1)
3.3.5 Visualization
85(2)
3.4 Verification and Sign-Off
87(12)
3.4.1 Extraction
87(3)
3.4.2 Power-Rail Analysis
90(9)
3.5 Modeling Thermomechanical-Stress-Related Issues in TSV
99(9)
3.5.1 New Thermomechanical Stress in a 3D TSV Stack
99(3)
3.5.2 TSV Stress-Induced Performance Modulation
102(1)
3.5.3 TSV Stress-Induced Reliability Concerns
102(2)
3.5.4 TSV Diameter Effects
104(2)
3.5.5 Insulation Material Effects
106(1)
3.5.6 TSV Material Effects
107(1)
3.6 Summary and Conclusions
108(2)
References
110(3)
4 Process Integration for TSV Manufacturing
113(42)
Sesh Ramaswami
4.1 Introduction
113(2)
4.2 Evolutionary Path to 3D Stacking
115(5)
4.2.1 Die Stacking
115(1)
4.2.2 Stacked Packages
115(1)
4.2.3 Micro-Bumps, Pillar and Re-Distribution Layers
116(1)
4.2.4 Interposers
117(1)
4.2.5 3D IC with TSV
118(2)
4.3 Stacking Methods
120(2)
4.4 TSV Process Overview
122(2)
4.4.1 TSV-Related Processing on Full-Thickness Wafers
123(1)
4.4.2 TSV-Related Processing on Thinned Wafers
123(1)
4.5 TSV Unit Processes
124(15)
4.5.1 Lithography
124(3)
4.5.2 TSV Etch, Photoresist Strip, and Wet Clean
127(1)
4.5.3 Insulator Deposition with Chemical Vapor Deposition
128(1)
4.5.4 Metal Barrier/Seed
129(1)
4.5.5 Via Fill
130(2)
4.5.6 Chemical Mechanical Polish (CMP) of Copper
132(1)
4.5.7 Wafer Bonding
133(3)
4.5.8 Wafer Thinning for TSV Processes
136(2)
4.5.9 Metrology and Inspection
138(1)
4.6 TSV-Integrated Processing
139(14)
4.6.1 Via-First TSVs
139(2)
4.6.2 Via-Middle TSVs
141(5)
4.6.3 Vias from the Topside
146(1)
4.6.4 Via-Last TSVs
147(1)
4.6.5 Via Reveal Process (Revealing the Via-Middle TSVs from the Backside)
148(4)
4.6.6 Summary
152(1)
References
153(2)
5 High-Aspect-Ratio Silicon Etch for TSV
155(78)
Banqiu Wu
Ajay Kumar
5.1 Introduction
155(4)
5.1.1 History of High-Aspect-Ratio (HAR) Silicon Etch
155(1)
5.1.2 HAR Silicon-Etch Applications
156(1)
5.1.3 HAR Silicon-Etch Methods
157(2)
5.2 Plasma-Etch Fundamentals
159(36)
5.2.1 Plasma Principles
159(8)
5.2.2 Plasma Sheath
167(6)
5.2.3 Mass-Transport Phenomena in Plasmas and TSV Etch
173(4)
5.2.4 Chemical Reactions and Kinetics
177(8)
5.2.5 Plasma Sources
185(6)
5.2.6 Plasma Diagnosis
191(4)
5.3 Time-Multiplexed Alternating Process
195(19)
5.3.1 Etch Rate and Selectivity
203(2)
5.3.2 Profile and Surface Roughness
205(2)
5.3.3 Aspect-Ratio-Dependent Etch (ARDE)
207(3)
5.3.4 Loading Effects
210(2)
5.3.5 Micrograss
212(1)
5.3.6 Notching
212(2)
5.4 Steady-State Etch Process
214(6)
5.4.1 Reactive Ion Etch (RIE)
214(1)
5.4.2 Etching at Cryogenic Condition
215(3)
5.4.3 Simultaneous Etch with Passivation
218(2)
5.5 Etch Method and Equipment
220(3)
5.5.1 RIE and Early Etchers
220(1)
5.5.2 Etchers Using Magnetic Field
221(1)
5.5.3 Inductively Coupled Plasma Etchers
222(1)
5.6 Summary
223(1)
References
224(9)
6 Dielectric Deposition for Through Silicon Vias
233(44)
Heung Lak Park
Ran Ding
Kedar Sapre
6.1 Introduction to Dielectric Films
233(2)
6.2 Key Requirements for Dielectric Process Used in 3D TSV
235(10)
6.2.1 Deposition Temperature
235(2)
6.2.2 Confomality of Dielectrics
237(4)
6.2.3 Hermeticity
241(1)
6.2.4 Electric Properties of Dielectrics
242(2)
6.2.5 Adhesion
244(1)
6.3 Fundamentals of Chemical Vapor Deposition (CVD)
245(4)
6.4 CVD Methods for TSV Application
249(22)
6.4.1 Atmospheric Pressure Chemical Vapor Deposition (APCVD)
249(2)
6.4.2 Low-Pressure CVD (LPCVD)
251(7)
6.4.3 Subatmospheric Chemical Vapor Deposition (SACVD)
258(2)
6.4.4 Plasma-Enhanced Chemical Vapor Deposition (PECVD)
260(11)
6.5 Summary
271(2)
References
273(4)
7 Barrier and Seed Deposition
277(32)
John Forster
Praburam Gopalraja
7.1 Introduction
277(1)
7.2 Material Choices
278(1)
7.3 Deposition Technologies
279(4)
7.3.1 Introduction
279(1)
7.3.2 Degas
280(1)
7.3.3 Pre-Clean
280(2)
7.3.4 CVD
282(1)
7.3.5 ALD
283(1)
7.3.6 PVD
283(1)
7.4 PVD Technology Details
283(14)
7.4.1 Introduction
283(4)
7.4.2 Ionized Metal Sources and Step Coverage
287(10)
7.5 TSV Application
297(6)
7.6 Conclusions
303(1)
Acknowledgments
303(1)
References
303(6)
8 Copper Electrodeposition for TSV
309(44)
Rozalia Beica
8.1 Introduction to Plating
309(11)
8.1.1 General Aspects
309(3)
8.1.2 Fundamentals
312(6)
8.1.3 History
318(2)
8.2 3D Chip Stacking Using Through Silicon Via
320(3)
8.2.1 General Overview of 3D Chip Stacking
320(1)
8.2.2 Plating Needs for 3D Chip Stacking
321(1)
8.2.3 Through Silicon Via Formation
322(1)
8.3 Copper Plating for TSV
323(25)
8.3.1 Advantages of Electrodeposition Processes
323(1)
8.3.2 Applications of Cu Plating for TSV
324(1)
8.3.3 Via-Processing Steps
325(2)
8.3.4 Success Criteria
327(1)
8.3.5 Key Factors
327(4)
8.3.6 Plating Chemistries
331(3)
8.3.7 Growth Mechanism
334(9)
8.3.8 TSV-Integration Challenges
343(2)
8.3.9 Equipment for Plating
345(3)
8.4 Summary
348(1)
Acknowledgments
349(1)
References
349(4)
9 Chemical Mechanical Polishing for TSV Applications
353(56)
Yuchun Wang
Max Gage
Wen-Chiang Tu
Lakshmanan Karuppiah
9.1 Introduction to CMP
353(5)
9.2 CMP Fundamentals
358(12)
9.2.1 Removal Rate and Film Properties
358(2)
9.2.2 Removal Profile Control with Hardware
360(1)
9.2.3 Planarization Efficiency
360(2)
9.2.4 Dishing, Erosion, and Corrosion versus Process Conditions
362(3)
9.2.5 Post-CMP Cleaning
365(4)
9.2.6 CMP Evolution and Disruptive Technologies
369(1)
9.3 Process Requirement for TSV versus Cu Damascene
370(4)
9.4 CMP Process Control and Metrology
374(5)
9.5 CMP Process for Different TSV-Integration Flows
379(6)
9.5.1 Cu CMP for Via-Middle
379(1)
9.5.2 CMP Process for Via-Last
380(2)
9.5.3 CMP Process Result for TSV
382(3)
9.6 Wafer Handling and Wafer-Backside Polishing for Via Reveal
385(8)
9.6.1 Handling of Bonded TSV Wafers
385(3)
9.6.2 Direct CMP of Si/Cu After Si Grinding
388(2)
9.6.3 CMP of Dielectric and Cu Nails After Passivation
390(3)
9.7 Further CMP-Process Variables and Characterization
393(5)
9.7.1 Local Pattern-Density Effect
393(2)
9.7.2 Effect of Cu-Plating Chemistry and Annealing on Cu-CMP Rates
395(1)
9.7.3 CMP Dishing Response to Different Barrier Metals
396(1)
9.7.4 Electrical Characterization Post CMP
397(1)
9.8 Post-CMP Defect Inspection
398(5)
9.8.1 In-Film Defects Between Cu Seed and ECD Cu
399(1)
9.8.2 Voids in Cu Vias
400(1)
9.8.3 CMP Residue
401(1)
9.8.4 Delamination and Arcing Defects
402(1)
9.9 Conclusions
403(1)
Acknowledgments
404(1)
References
404(5)
10 Temporary and Permanent Bonding
409(28)
Bioh Kim
Matthias Thorsten
Dragoi Viorel
Markus Wimplinger
Paul Lindner
10.1 Introduction to Wafer Bonding for TSV Integration
409(1)
10.2 Wafer-to-Wafer Alignment and Bonding for TSV Integration
410(13)
10.2.1 Introduction
410(2)
10.2.2 Wafer-to-Wafer Alignment
412(5)
10.2.3 Wafer Bonding for TSV Integration
417(6)
10.3 Comparison of Stacking Schemes: W2W, C2W, and Advanced C2W
423(4)
10.4 Temporary Bonding and Debonding for Thin-Wafer Handling and Processing
427(6)
References
433(4)
11 Assembly and Test Aspects of TSV Technology
437(56)
Robert Darveaux
Rick Reed
Ki Wook Lee
Mark Berry
Ron Huemoeller
Seong Min Seo
Jesse Galloway
Nozad Karim
Jae Dong Kim
Choon Heung Lee
11.1 Introduction
437(3)
11.2 Process Integration
440(24)
11.2.1 TSV Wafer Finishing
440(11)
11.2.2 Assembly
451(3)
11.2.3 Test Strategies for Advanced SiP and 3D/TSV Packages
454(10)
11.3 TSV Logistics and Supply-Chain Issues
464(7)
11.4 TSV Design Considerations for Wafer-Backside Bumping
471(3)
11.5 Thermal Performance of TSV Packages
474(3)
11.6 Reliability Considerations for TSV Packages
477(4)
11.7 Electrical Performance of TSV Packages
481(7)
11.8 Summary and Conclusions
488(2)
References
490(3)
Index 493
Banqiu Wu is Chief Technology Officer, TSV and Mask Products Business Group, Applied Materials, Inc. Dr. Wu has published over 50 technological papers in 10 peer-reviewed journals and conference proceedings, and authored/co-authored several books, including Photomask Fabrication Technology and Extreme Ultraviolet Lithography. He holds multiple patents and awards.





Dr. Ajay Kumar is Vice President and General Manager of TSV and Mask Products Business Group, Applied Materials, Inc. He has more than 75 publications to his credit in various journals including several review articles. Dr. Kumar co-authored the book Extreme Ultraviolet Lithography. He holds more than 100 US patents and has won many awards for innovation and commercialization.





Sesh Ramaswami is a senior director of TSV strategy and marketing at Applied Materials, Inc. His responsibilities include TSV and associated wafer level processing for packaging. Ramaswami holds 35 US patents and has 40+ conference publications and presentations in conferences such as MRS, ECS, VMIC, AVS, SPIE and IRPS.
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