Atnaujinkite slapukų nuostatas

El. knyga: Advances In 3d Integrated Circuits And Systems

(Ntu, S'pore), (Ntu, S'pore)
Kitos knygos pagal šią temą:
Advances In 3d Integrated Circuits And SystemsDidesnis paveikslėlis
Kitos knygos pagal šią temą:

DRM apribojimai

  • Kopijuoti:

    neleidžiama

  • Spausdinti:

    neleidžiama

  • El. knygos naudojimas:

    Skaitmeninių teisių valdymas (DRM)
    Leidykla pateikė šią knygą šifruota forma, o tai reiškia, kad norint ją atrakinti ir perskaityti reikia įdiegti nemokamą programinę įrangą. Norint skaityti šią el. knygą, turite susikurti Adobe ID . Daugiau informacijos  čia. El. knygą galima atsisiųsti į 6 įrenginius (vienas vartotojas su tuo pačiu Adobe ID).

    Reikalinga programinė įranga
    Norint skaityti šią el. knygą mobiliajame įrenginyje (telefone ar planšetiniame kompiuteryje), turite įdiegti šią nemokamą programėlę: PocketBook Reader (iOS / Android)

    Norint skaityti šią el. knygą asmeniniame arba „Mac“ kompiuteryje, Jums reikalinga  Adobe Digital Editions “ (tai nemokama programa, specialiai sukurta el. knygoms. Tai nėra tas pats, kas „Adobe Reader“, kurią tikriausiai jau turite savo kompiuteryje.)

    Negalite skaityti šios el. knygos naudodami „Amazon Kindle“.

3D integration is an emerging technology for the design of many-core microprocessors and memory integration. This book, Advances in 3D Integrated Circuits and Systems, is written to help readers understand 3D integrated circuits in three stages: device basics, system level management, and real designs.Contents presented in this book include fabrication techniques for 3D TSV and 2.5D TSI; device modeling; physical designs; thermal, power and I/O management; and 3D designs of sensors, I/Os, multi-core processors, and memory.Advanced undergraduates, graduate students, researchers and engineers may find this text useful for understanding the many challenges faced in the development and building of 3D integrated circuits and systems.
Preface v
1 Introduction
1(16)
1.1 Thousand-core On-chip
1(4)
1.2 State-of-the-Art Many-core Microprocessors
5(2)
1.3 Memory-logic Integration
7(8)
1.3.1 2D Integration Challenges
7(5)
1.3.1.1 Scalability
7(1)
1.3.1.2 Channel Loss
8(2)
1.3.1.3 I/O Circuit Design
1.3.1.4 Testing
10(1)
1.3.1.5 Thermal Management
10(1)
1.3.1.6 Power Management
11(1)
1.3.1.7 I/O Management
11(1)
1.3.2 3D Integration
12(2)
1.3.3 2.5D Integration
14(1)
1.4 Organization of the Book
15(2)
Part 1 Device Modeling 17(82)
2 Fabrication
19(52)
2.1 Introduction
19(2)
2.2 TSV Structure and Fabrication
21(16)
2.2.1 Structure Design
21(4)
2.2.1.1 Wafer Layout and Mask Design
21(1)
2.2.1.2 Electrical Structure Design
22(2)
2.2.1.3 Thermal Structure Design
24(1)
2.2.1.4 Dummy TSV Blocks
25(1)
2.2.2 Fabrication Process
25(5)
2.2.2.1 Electrical Structure Fabrication Process
25(3)
2.2.2.2 Thermal Structure Fabrication Process
28(2)
2.2.3 Process Control and Optimization
30(7)
2.2.3.1 DRIE Si Etch
30(1)
2.2.3.2 Dielectric Liner Deposition
31(2)
2.2.3.3 Ta Barrier/Cu Seed Layer Deposition and Cu ECP
33(2)
2.2.3.4 Cu CMP
35(2)
2.3 TSV Electrical Characterization
37(17)
2.3.1 Measurement Setup
37(1)
2.3.2 Conventional PETEOS Oxide Liner
38(4)
2.3.2.1 Electrical CV Measurement
38(4)
2.3.2.2 Electrical IV Measurement
42(1)
2.3.3 Black Diamond Low-k Liner
42(6)
2.3.3.1 Electrical CV Measurement
44(2)
2.3.3.2 Electrical IV Measurement
46(2)
2.3.4 Al2O3/Oxide Bi-layer Liner
48(6)
2.3.4.1 Electrical CV Measurement
48(5)
2.3.4.2 Electrical IV Measurement
53(1)
2.4 TSV Thermal Characterization Results
54(10)
2.4.1 Measurement Setup
54(1)
2.4.2 Cu-TSV Thermal Modeling
55(1)
2.4.3 Cu-TSV Induced Stress Modeling
56(5)
2.4.4 Cu-TSV Induced Stress Measurement by Micro-Raman Analysis
61(3)
2.5 TSI Structure and Fabrication
64(5)
2.5.1 Structure Design
65(3)
2.5.2 Fabrication Process
68(1)
2.6 Summary
69(2)
3 Device Model
71(28)
3.1 Introduction
71(1)
3.2 Nonlinear MOSCAP Model
72(3)
3.3 TSV Device Model
75(16)
3.3.1 Electrical Model
75(2)
3.3.2 Thermal Model
77(5)
3.3.3 Mechanical Model
82(4)
3.3.4 Delay Model
86(4)
3.3.4.1 Electrical-Thermal Coupled Delay Model
86(1)
3.3.4.2 Electrical-Mechanical Coupled Delay Model
87(1)
3.3.4.3 Electrical-Thermal-Mechanical Coupled Delay Model
88(2)
3.3.5 Power Model
90(1)
3.4 TSI Device Model
91(6)
3.4.1 Delay Model
92(2)
3.4.1.1 T-line Model
92(1)
3.4.1.2 Delay of T-line
93(1)
3.4.2 Power Model
94(11)
3.4.2.1 TSV and TSI Comparison
95(1)
3.4.2.2 Energy-efficiency Analysis
95(2)
3.5 Summary
97(2)
Part 2 Physical Design 99(56)
4 Macromodel
101(12)
4.1 Introduction
101(2)
4.2 Power and Thermal Integrity
103(2)
4.3 Macromodeling
105(6)
4.3.1 Complexity Compression
106(3)
4.3.1.1 Complexity Compression of States
106(1)
4.3.1.2 Complexity Compression of I/Os
107(2)
4.3.2 Parameterization
109(2)
4.4 Summary
111(2)
5 TSV Allocation
113(26)
5.1 Introduction
113(1)
5.2 Power Ground Design
114(8)
5.2.1 Problem Formulation
114(2)
5.2.2 Sensitivity based TSV Allocation
116(6)
5.3 Clock-tree Design
122(15)
5.3.1 Problem Formulation
123(1)
5.3.2 Sensitivity based TSV Allocation
123(17)
5.3.2.1 Reduction of Thermal Gradient
124(2)
5.3.2.2 Reduction of Stress Gradient
126(2)
5.3.2.3 Clock-skew Reduction
128(9)
5.4 Summary
137(2)
6 Testing
139(16)
6.1 Introduction
139(1)
6.2 3D IC Test
140(3)
6.2.1 System Architecture
140(2)
6.2.2 Problem Formulation
142(1)
6.3 Compressive Sensing and Recovery of Testing Data
143(4)
6.3.1 Sparsity of Test Data
143(2)
6.3.2 Lossless Compression and Recovery
145(1)
6.3.3 OMP Solver
146(1)
6.4 TSV Testing
147(6)
6.4.1 Testing Circuit
147(2)
6.4.2 Pre-bond TSV Test
149(3)
6.4.3 Post-bond TSV Test
152(1)
6.5 Summary
153(2)
Part 3 Thermal Management 155(40)
7 Power and Thermal System Model
157(18)
7.1 Introduction
157(2)
7.2 3D System Power Model
159(5)
7.2.1 Core and DRAM Power Model
159(1)
7.2.2 System Power Breakdown
160(4)
7.2.2.1 Thermal Runaway Failure
162(2)
7.3 3D System Thermal Model
164(7)
7.3.1 Microfluidic Channel Thermal Model
166(1)
7.3.2 Steady State Thermal Analysis
167(4)
7.3.2.1 Software Implementation
168(1)
7.3.2.2 Validation of Proposed Model
169(2)
7.4 3D Cyber-physical System
171(2)
7.4.1 System Architecture
171(1)
7.4.2 Problem Formulation
172(1)
7.5 Summary
173(2)
8 Microfluidic Based Cooling
175(20)
8.1 Introduction
175(1)
8.2 3D Cyber-physical Thermal Management
176(17)
8.2.1 Real-time Temperature Demand Estimation
179(1)
8.2.2 Prediction and Correction
179(3)
8.2.3 Clustering of Microchannels
182(7)
8.2.4 Allocation of Flow Rates
189(2)
8.2.5 Minimization of Cooling Effort
191(2)
8.3 Summary
193(2)
Part 4 I/O Management 195(154)
9 Power I/O Management
197(32)
9.1 Introduction
197(2)
9.2 3D Power I/O Management
199(6)
9.2.1 System Architecture
200(4)
9.2.2 Problem Formulation
204(1)
9.3 ILP based Optimization
205(1)
9.4 Space-time Multiplexing
206(21)
9.4.1 Adaptive Clustering
207(14)
9.4.1.1 Power-signature Extraction
207(3)
9.4.1.2 Space Multiplexing: Grouping
210(1)
9.4.1.3 Time Multiplexing: Subgrouping
211(1)
9.4.1.4 Allocation of Power Converters
212(9)
9.4.2 Scheduling of Workloads
221(10)
9.4.2.1 Slack Calculation
222(2)
9.4.2.2 Scheduling of Workloads
224(3)
9.5 Summary
227(2)
10 Signal I/O Management
229(34)
10.1 Introduction
229(2)
10.2 3D Bandwidth and Voltage-swing Management
231(4)
10.2.1 System Architecture
231(1)
10.2.2 Problem Formulation
232(3)
10.3 Signal I/O Bandwidth Management
235(10)
10.3.1 Memory-access Data-pattern
235(3)
10.3.1.1 LLC MPKI Pattern
235(2)
10.3.1.2 Quality of Service
237(1)
10.3.2 Reconfigurable Memory Controller
238(7)
10.3.2.1 Space Multiplexing: Channel Allocation
238(1)
10.3.2.2 Time Multiplexing: Time-slot Allocation
238(1)
10.3.2.3 Space-Time Multiplexing based I/O Bandwidth Management
239(6)
10.4 Signal I/O Voltage-swing Management
245(16)
10.4.1 Reinforcement Q-learning
248(17)
10.4.1.1 Q-learning Theory
248(2)
10.4.1.2 System Model
250(1)
10.4.1.3 Adaptive I/O Voltage-swing Tuning
251(3)
10.4.1.4 Accelerated Q-learning
254(5)
10.4.1.5 Comparison of Adaptive Tuning by Conventional and Accelerated Q-learning
259(2)
10.5 Summary
261(2)
11 Sensor
263(18)
11.1 Introduction
263(2)
11.2 3D Sensor Design
265(7)
11.2.1 SOI MEMS Accelerometer
265(3)
11.2.2 CMOS Readout Circuit
268(4)
11.3 Testing and Measurement
272(6)
11.3.1 Hermetic Test
273(4)
11.3.2 Bonding Reliability
277(1)
11.3.3 Measurement Results
277(1)
11.4 Summary
278(3)
12 I/O
281(24)
12.1 Introduction
281(2)
12.2 2.5D I/O Buffer Design
283(8)
12.2.1 LVDS I/O Buffer
284(2)
12.2.2 CML I/O Buffer
286(1)
12.2.3 Simulation Results
287(4)
12.2.3.1 EM Simulation of TSV and TSI I/O
290(1)
12.3 2.5D Adaptive I/O
291(7)
12.3.1 Transmitter and Receiver
293(3)
12.3.1.1 Error Correcting Code
295(1)
12.3.2 Simulation Results
296(2)
12.4 2.5D I/O with Clock Data Recovery
298(6)
12.4.1 CTLE Equalization
298(1)
12.4.2 Current Sampling
299(1)
12.4.3 Phase Interpolator
300(1)
12.4.4 Measurement Results
301(6)
12.4.4.1 Data Recovery
301(1)
12.4.4.2 Clock Recovery
302(2)
12.5 Summary
304(1)
13 Microprocessor
305(18)
13.1 Introduction
305(2)
13.2 Building Blocks
307(11)
13.2.1 Core
307(2)
13.2.2 Router
309(3)
13.2.2.1 Core-to-core Communication
310(1)
13.2.2.2 Core-to-memory Communication
311(1)
13.2.3 Accelerator
312(2)
13.2.4 I/O Link
314(4)
13.2.4.1 Transmitter
315(1)
13.2.4.2 Receiver
315(2)
13.2.4.3 Voltage-controlled Oscillator
317(1)
13.3 2.5D Multi-core Microprocessor
318(3)
13.3.1 System Design
318(1)
13.3.2 Fabricated Chip
318(1)
13.3.3 Simulation Results
318(3)
13.4 Summary
321(2)
14 Non-volatile Memory
323(26)
14.1 Introduction
323(1)
14.2 3D Hybrid Memory with ReRAM
324(2)
14.3 ReRAM-crossbar Memory Design
326(14)
14.3.1 Performance Modeling
331(6)
14.3.1.1 Delay Model
331(3)
14.3.1.2 Power Model
334(2)
14.3.1.3 Area Model
336(1)
14.3.1.4 Stacked CBRAM-crossbar Memory
337(1)
14.3.2 Design Space Exploration
337(3)
14.4 ReRAM Block-level Incremental Data Retention
340(7)
14.4.1 Dirty Bit Set-up
341(1)
14.4.2 Incremental Write-back
342(2)
14.4.3 Simulation Results
344(3)
14.5 Summary
347(2)
Bibliography 349(24)
Index 373
Daugiau apie elektronines knygas Daugiau apie elektronines knygas
Pastovi nuoroda: https://www.kriso.lt/db/97898146990376e.html
Raktažodžiai: