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Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques 2010 ed. [Kietas viršelis]

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  • Formatas: Hardback, 240 pages, aukštis x plotis: 235x155 mm, weight: 1190 g, 141 Illustrations, black and white; 240 p. 141 illus., 1 Hardback
  • Serija: Studies in Computational Intelligence 294
  • Išleidimo metai: 22-Apr-2010
  • Leidėjas: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
  • ISBN-10: 3642123457
  • ISBN-13: 9783642123450
Kitos knygos pagal šią temą:
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques 2010 ed.Didesnis paveikslėlis
  • Formatas: Hardback, 240 pages, aukštis x plotis: 235x155 mm, weight: 1190 g, 141 Illustrations, black and white; 240 p. 141 illus., 1 Hardback
  • Serija: Studies in Computational Intelligence 294
  • Išleidimo metai: 22-Apr-2010
  • Leidėjas: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
  • ISBN-10: 3642123457
  • ISBN-13: 9783642123450
Kitos knygos pagal šią temą:
Pastovi nuoroda: https://www.kriso.lt/db/9783642123450.html
Raktažodžiai:
The microelectronics market, with special emphasis to the production of complex mixed-signal systems-on-chip (SoC), is driven by three main dynamics, time-- market, productivity and managing complexity. Pushed by the progress in na- meter technology, the design teams are facing a curve of complexity that grows exponentially, thereby slowing down the productivity design rate. Analog design automation tools are not developing at the same pace of technology, once custom design, characterized by decisions taken at each step of the analog design flow, - lies most of the time on designer knowledge and expertise. Actually, the use of - sign management platforms, like the Cadences Virtuoso platform, with a set of - tegrated CAD tools and database facilities to deal with the design transformations from the system level to the physical implementation, can significantly speed-up the design process and enhance the productivity of analog/mixed-signal integrated circuit (IC) design teams. These design management platforms are a valuable help in analog IC design but they are still far behind the development stage of design automation tools already available for digital design. Therefore, the development of new CAD tools and design methodologies for analog and mixed-signal ICs is ess- tial to increase the designers productivity and reduce design productivitygap. The work presented in this book describes a new design automation approach to the problem of sizing analog ICs.
1 Introduction
1(18)
1.1 Microelectronics Market and Technology Evolution
1(2)
1.2 Analog Integrated Circuit Design
3(7)
1.2.1 Analog Design Issues
3(1)
1.2.2 The Hierachical Decomposition Model
4(1)
1.2.3 Analog IC Design Flow
5(3)
1.2.4 Analog Design Flow of a 15-Bit Pipeline CMOS A/D Coverter
8(2)
1.3 Anolog Design Automation
10(9)
1.3.1 CAD Tools for Analog Circuit Design
10(1)
1.3.2 Automated Analog IC Design
11(3)
References
14(5)
2 State-of-the-Art on Analog Design Automation
19(30)
2.1 Trends in Design Automation Methodology
19(7)
2.1.1 Automated Topology Selection
20(3)
2.1.2 Automated Circuit Siozing/Optimization
23(1)
2.1.3 Automated Layout Generation
23(3)
2.2 Automated Circuit Synthesis Approaches
26(5)
2.2.1 Knowledge-Based Approach
26(1)
2.2.2 Optimization-Based Approach
27(1)
2.2.2.1 Equation-Based Methods
28(1)
2.2.2.2 Simulation-Based Methods
29(1)
2.2.2.3 Learning-Based Methods
30(1)
2.2.3 Commercial Tools
31(1)
2.3 Design Automation Tools: Comparative Analysis
31(11)
2.3.1 Specific Characteristics
36(1)
2.3.2 Performance Analysis
37(1)
2.2.3 Optimization Techniques
38(2)
2.3.4 Other Characteristics
40(1)
2.3.5 Summary
40(2)
2.4 GENOM Optimization Tool: Implentation Goals
42(1)
2.5 Conclusions
43(6)
References
44(5)
3 Evolutionary Analog IC Design Optimization
49(40)
3.1 Computation Techniques for Analog IC Design-An Overview
49(8)
3.1.1 Analog IC Design Problem Formulation
49(2)
3.1.2 Numeric Programming Techniques
51(1)
3.1.3 The No-Free-Lunch Theorem
52(2)
3.1.4 Evolutionary Computation Techniques Overview
54(3)
3.2 Key Issues in Evolutionary Search
57(4)
3.3 GENOM-Evolutionary Kernel for Analog IC Design Optimization
61(23)
3.3.1 Finess Function Study
61(1)
3.3.1 Multi-objective Cost Function
62(3)
3.3.1.2 Cost Function with No Preference Articulation
65(2)
3.3.2 Individual Encoding, Population Structure and Sampling
67(4)
3.3.3 Selection Strategies
71(1)
3.3.3.1 Ranking- Based Scheme
71(1)
3.3.3.2 Constraint- Based Selection
72(1)
3.3.4 Crossover Strategies
73(1)
3.3.5 Mutation Strategies
74(2)
3.3.6 Step Size Control- Dynamic Evolutionary Control
76(1)
3.3.7 A Distributed Algorithm for Time Consuming Fitness Functions
77(3)
3.3.8 GENOM GA Attributes
80(2)
3.3.9 GENOM Optimization Methodology
82(1)
3.3.9.1 Optimization Setup
82(1)
3.3.9.2 Coarse Optimization
83(1)
3.3.9.3 Fine-Tuning Optimization
83(1)
3.4 Conclusions
84(5)
References
84(5)
4 Enhanced Techniquess for Analog Circuits Design Using SVM Models
89(20)
4.1 Learning Algorithms Overview
89(7)
4.1.1 SVM Cassification Overview
95(1)
4.2 GA-SVM Optimization Approach
96(9)
4.2.1 Feasibility Region Definition
96(2)
4.2.2 Methodology Overview
98(2)
4.2.3 The Feasibility Model Formulation
100(1)
4.2.4 SVM Model Generation and Improvement
101(1)
4.2.5 Handling Unbalanced Data in Circuit Designs
102(2)
4.2.6 GA- SVM Optimization Overview
104(1)
4.2.7 Comments on the Methodology
105(1)
4.3 Conclusions
105(4)
References
106(3)
5 Analog IC Design Environment Architecture
109(30)
5.1 AIDA Architecture
109(3)
5.1.1 AIDA In-House Design Environment Overview
109(3)
5.1.2 Layout Level Tools
112(1)
5.2 GENOM System Overview
112(16)
5.2.1 Design Flow
113(1)
5.2.2 Input Data
114(6)
5.2.3 Output Data
120(1)
5.2.3.1 Progress Real-Time Reports
121(1)
5.2.3.2 Interactive Design
122(1)
5.2.4 I/O Interfaces
123(2)
5.2.5 Evaluation Engine
125(1)
5.2.6 Expansion of GENOM Tool
125(2)
5.2.7 Optimization Kernel Configuration
127(1)
5.3 Data Flow Management
128(8)
5.3.1 Input Data Specification
129(2)
5.3.2 Evaluation/Simulation Data Hardware
131(2)
5.3.3 Output Data
133(1)
5.3.3.1 The Simulation and Equation Based Cost Function Parser
134(2)
5.4 Conclusions
136(3)
References
137(2)
6 Optimization of Analog Circuits and System-Applications
139(48)
6.1 Testing the Performance of Analog Circuits
139(2)
6.2 Testing the GENOM-Selected Circuit Topologies
141(3)
6.3 GENOM Convergence Tests
144(4)
6.3.1 The Analog IC Design Approach
145(1)
6.3.2 Testing the Selection Approach
146(2)
6.4 Comparing GA-STD, GA-MOD and GA-SVM Performance
148(8)
6.4.1 GA-STD versus GA-SVM Performance-Filter Case Study
149(2)
6.4.2 Static GA-SVM Performance-OpAmp Case Study
151(2)
6.4.2.1 Evaluation Metric
153(1)
6.4.3 Testing the Dynamic GA-SVM Performance
154(2)
6.4.4 Final Comments
156(1)
6.5 General Purpose Circuits or High Performance Circuits Design
156(22)
6.5.1 Fully Differential OpAmp
157(1)
6.5.1.1 Performance Specifications, Input Variables Ranges and Design Space Size
158(2)
6.5.1.2 Analysis
160(3)
6.5.1.3 Design Analysis
163(1)
6.5.2 A Common OTA Fully Differential Telescopic OpAmp
164(1)
6.5.2.1 Description
164(1)
6.5.2.2 Problem Specifications and Design Configurations
165(2)
6.5.2.3 Analysis
167(3)
6.5.2.4 Design Analysis
170(2)
6.5.3 Folded Cascode OpAmp with AB Output
172(1)
6.5.3.1 Description
172(1)
6.5.3.2 Problem Specifications and Design Configurations
173(2)
6.5.3.3 Design Analysis
175(3)
6.6 Comparison with Other Tools/Approaches
178(7)
6.6.1 FRIDGE Benchmark Circuit Tests
179(1)
6.6.2 Optimization Test with FRIDGE Ampop
179(3)
6.6.3 Comparison Results
182(1)
6.6.4 Corners Optimization with FRIDGE Circuit
183(2)
6.7 Conclusions
185(2)
References
185(2)
7 Conclusion
187(4)
7.1 Conclusions
187(1)
7.2 Future Work
188(3)
Appendixes
191(36)
Appendix A Terminology
191(2)
Appendix B General Purpose Optimization Techniques
193(6)
B.1 Random Search Methods
193(1)
B.2 Unconstrained Gradient-Based Methods
193(1)
B.3 Constraints Programming
194(1)
B.4 Direct Stochastic Methods
195(2)
B.5 Multiple Objectives
197(2)
Appendix C The Basic Decisions of Standard GA Algorithms
199(14)
C.1 Standard GA Kernel Optimization
199(1)
C.1.1 Evolutionary Kernel Framework
199(1)
C.1.2 Algorithm Design Parameters
200(2)
C.1.3 Single Optimization GA Example
202(3)
C.2 Representation and Encoding
205(1)
C.3 Fitness Evaluation and Assignment
206(1)
C.4 Initial Population
207(1)
C.5 Selection
208(1)
C.6 Crossover Operator
209(2)
C.7 Mutation Operator
211(1)
C.8 Performance Criteria
212(1)
Appendix D Support Vector Machine Overview
213(14)
D.1 The SVM Model Formulation
213(2)
D.2 Data Setup
215(1)
D.2.1 Data Collection
215(1)
D.2.2 Pre-Processing of the Training Data
216(1)
D.2.3 Unbalanced Data Sets
216(1)
D.3 SVM Model Building
217(1)
D.3.1 Training and Testing by Simple Validation Approach
218(1)
D.3.2 Bootstrap Method
218(1)
D.3.3 Cross-Validation Method
218(1)
D.4 SVM Model Evaluation
219(1)
D.4.1 Kernel Evaluation Metrics
219(1)
D.4.2 Model Selection Parameters
220(2)
References
222(5)
Index 227