As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances.
As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends.
The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix.
| About the authors |
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xi | |
| Preface |
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xiii | |
| Acknowledgments |
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xv | |
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1 | (4) |
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2 Introduction to phase noise and jitter |
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5 | (12) |
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5 | (2) |
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2.2 Power spectral density |
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7 | (3) |
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7 | (1) |
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2.2.2 Sine wave with narrowband phase modulation |
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7 | (2) |
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2.2.3 Sine wave with both jitter and noise |
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9 | (1) |
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10 | (2) |
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2.4 Relation of phase noise and jitter |
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12 | (3) |
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15 | (2) |
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17 | (14) |
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17 | (4) |
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21 | (6) |
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3.3 Appendix: Translation of series R-L to parallel R-L |
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27 | (1) |
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28 | (3) |
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4 Phase noise theory for CMOS oscillators |
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31 | (20) |
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4.1 Linear time-invariant phase noise model |
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31 | (6) |
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4.2 Time-varying phase noise model |
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37 | (12) |
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49 | (2) |
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5 Introduction to PLL/DLL |
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51 | (34) |
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5.1 Applications of PLL/DLL |
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51 | (3) |
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54 | (20) |
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5.2.1 Voltage-controlled oscillator |
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54 | (4) |
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58 | (9) |
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5.2.3 Charge pump and loop filter |
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67 | (4) |
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71 | (3) |
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74 | (1) |
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5.4 False locking and failure issues in PLL/DLL |
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75 | (6) |
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81 | (4) |
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6 PLL loop dynamics and jitter |
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85 | (30) |
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6.1 Transfer function of PLL building blocks |
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85 | (2) |
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87 | (19) |
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87 | (4) |
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6.2.2 Tuning design parameters |
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91 | (1) |
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92 | (5) |
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6.2.4 Reference spur and static phase error |
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97 | (3) |
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100 | (3) |
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103 | (3) |
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6.3 Supply noise-induced jitter |
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106 | (5) |
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6.3.1 Impact of supply noise to PLL jitter |
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106 | (2) |
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6.3.2 Supply-induced jitter reduction techniques |
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108 | (3) |
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Appendix A Analytic expression of the reference spur |
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111 | (1) |
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Appendix B Why do we use PLL rather than FLL for frequency generation? |
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112 | (1) |
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113 | (2) |
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7 DLL loop dynamics and jitter |
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115 | (20) |
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115 | (1) |
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115 | (9) |
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7.2.1 Input jitter transfer |
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115 | (7) |
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7.2.2 Jitter transfer of VCDL jitter and PD/CP noise |
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122 | (2) |
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7.3 Jitter generation and transfer of open-loop clock buffer |
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124 | (7) |
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7.4 Design consideration on number of stages and tuning range of DLL |
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131 | (2) |
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133 | (2) |
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8 Phase noise suppression techniques 1: subsampling PLL |
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135 | (12) |
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135 | (1) |
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136 | (8) |
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144 | (1) |
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145 | (2) |
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9 Phase noise suppression techniques 2: all-digital PLL |
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147 | (22) |
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147 | (1) |
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9.2 ADPLL building blocks |
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148 | (15) |
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9.2.1 Digital loop filter |
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148 | (2) |
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9.2.2 Time-to-digital converter |
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150 | (9) |
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9.2.3 Digitally controlled oscillator |
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159 | (4) |
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9.3 Quantization noise and jitter |
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163 | (2) |
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9.3.1 Linearized model of ADPLL |
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163 | (1) |
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9.3.2 Quantization noise of TDC |
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164 | (1) |
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9.3.3 Quantization noise of DCO |
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165 | (1) |
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165 | (4) |
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10 Phase noise suppression techniques 3: injection locking |
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169 | (18) |
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10.1 Injection locking basics |
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169 | (2) |
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10.2 Jitter transfer of ILO |
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171 | (1) |
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172 | (2) |
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10.4 ILO circuit implementation |
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174 | (6) |
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10.5 Injection-locked PLL |
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180 | (5) |
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185 | (2) |
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11 Phase noise suppression techniques 4: clock multiplying DLL |
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187 | (10) |
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11.1 DLL with an edge-combining logic |
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187 | (1) |
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187 | (4) |
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11.3 Offset compensation techniques |
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191 | (2) |
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11.4 Fractional-N MDLL and ILO |
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193 | (2) |
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195 | (2) |
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Appendix A Figure of merits (FoMs) for evaluating VCOs and PLLs |
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197 | (6) |
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201 | (2) |
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Appendix B Survey on state-of-the-art clock generators |
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203 | (18) |
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211 | (10) |
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Appendix C System Verilog modeling of CMOS clock generator including jitter |
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221 | (8) |
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228 | (1) |
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Appendix D Noise sources in MOSFET transistor |
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229 | (4) |
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231 | (2) |
| Index |
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233 | |
Woorham Bae received the B.S. and Ph.D. degrees in Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2010 and 2016, respectively. In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. From 2017 to 2019, he was with the University of California, Berkeley, CA, as a Postdoctoral Researcher. He is currently a Senior SerDes Engineer with Ayar Labs, Santa Clara, CA. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, nonvolatile memory systems, and agile hardware design methodology. Dr. Bae received the IEEE Circuits and Systems Society Outstanding Young Author Award in 2018, the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 2016, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 2016, and the IEEE Solid-State Circuits Society STG Award in 2015.
Deog-Kyoon Jeong received the B.S. and M.S. degrees in Electronics Engineering from Seoul National University, Seoul, South Korea, in 1981 and 1984, respectively, and the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California at Berkeley, Berkeley, CA, USA, in 1989. From 1989 to 1991, he was a member of the Technical Staff with Texas Instruments, Dallas, TX, USA. He worked on the modeling and design of BiCMOS gates and the single-chip implementation of the SPARC architecture. Then, he joined the faculty of the Department of Electronics Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, where he is currently an Endowed-Chair Professor. He was one of cofounders of Silicon Image, Sunnyvale, CA, now Lattice Semiconductor, which specialized in digital interface circuits for video displays such as DVI and HDMI. His main research interests include the design of high-speed I/O circuits, phase-locked loops, and memory system architecture. Dr. Jeong was a recipient of the ISSCC Takuo Sugano Award in 2005 for Outstanding Far-East Paper. He is a Fellow of the IEEE.
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