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Counterfeit Integrated Circuits: Detection and Avoidance [Kietas viršelis]

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  • Formatas: Hardback, 269 pages, aukštis x plotis: 235x155 mm, weight: 6149 g, 109 Illustrations, color; 25 Illustrations, black and white; XX, 269 p. 134 illus., 109 illus. in color., 1 Hardback
  • Išleidimo metai: 19-Mar-2015
  • Leidėjas: Springer International Publishing AG
  • ISBN-10: 3319118234
  • ISBN-13: 9783319118239
Kitos knygos pagal šią temą:
Counterfeit Integrated Circuits: Detection and AvoidanceDidesnis paveikslėlis
  • Formatas: Hardback, 269 pages, aukštis x plotis: 235x155 mm, weight: 6149 g, 109 Illustrations, color; 25 Illustrations, black and white; XX, 269 p. 134 illus., 109 illus. in color., 1 Hardback
  • Išleidimo metai: 19-Mar-2015
  • Leidėjas: Springer International Publishing AG
  • ISBN-10: 3319118234
  • ISBN-13: 9783319118239
Kitos knygos pagal šią temą:
Pastovi nuoroda: https://www.kriso.lt/db/9783319118239.html
Raktažodžiai:
This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade.  The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs).  Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat.

 

·      Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem;

·      Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation;

·      Provides step-by-step solutions for detecting different types of counterfeit ICs;

·      Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC detection and avoidance, for industry and government.

Recenzijos

In this book, the authors present an overall description of the physical and electrical techniques that are used in the state of the art. Those techniques are proven to be useful in the practical detection and avoidance of counterfeit ICs. usable as a handbook for engineers and experts in this field. (Zheng Gong, computing Reviews, August, 2015)

1 Introduction 1(14)
1.1 History of Counterfeiting
2(1)
1.2 Counterfeit Products
3(1)
1.3 Counterfeits: A Trillion Dollar Market and Beyond
4(1)
1.4 Counterfeit Electronics: An Emerging Threat
5(7)
1.4.1 Defense Industrial Base Assessment: Counterfeit Electronics
9(3)
1.5 Summary
12(2)
References
14(1)
2 Counterfeit Integrated Circuits 15(22)
2.1 Counterfeit IC Types
17(1)
2.2 Taxonomy of Counterfeit Types
18(9)
2.2.1 Recycled
19(2)
2.2.2 Remarked
21(1)
2.2.3 Overproduced
22(1)
2.2.4 Out-of-Spec/Defective
23(2)
2.2.5 Cloned
25(1)
2.2.6 Forged Documentation
25(1)
2.2.7 Tampered
26(1)
2.3 Supply Chain Vulnerabilities
27(2)
2.3.1 Design
27(1)
2.3.2 Fabrication
28(1)
2.3.3 Assembly
28(1)
2.3.4 Distribution
28(1)
2.3.5 System Integration/Lifetime
29(1)
2.3.6 End-of-Life
29(1)
2.4 Detection and Avoidance of Counterfeit ICs
29(4)
2.4.1 Current Status of Detection
30(2)
2.4.2 Current Status of Avoidance
32(1)
2.5 Summary
33(1)
References
34(3)
3 Counterfeit Defects 37(38)
3.1 Taxonomy of Counterfeit Defects
38(1)
3.2 Procedural Defects
38(5)
3.3 Mechanical Defects
43(20)
3.3.1 Leads, Balls and Columns
44(6)
3.3.2 Package
50(6)
3.3.3 Bond Wires
56(3)
3.3.4 Die
59(4)
3.4 Environmental Defects
63(2)
3.5 Electrical Defects
65(6)
3.5.1 Parametric Defects
66(3)
3.5.2 Manufacturing Defects
69(2)
3.6 Summary
71(1)
References
72(3)
4 Physical Tests for Counterfeit Detection 75(20)
4.1 Taxonomy of Counterfeit Detection Methods
76(2)
4.2 Physical Inspection
78(1)
4.2.1 External Visual Inspection (EVI)
78(12)
4.2.2 X-Ray Imaging
81(2)
4.2.3 Delid/Decapsulation
83(1)
4.2.4 Scanning Acoustic Microscopy (SAM)
83(2)
4.2.5 Scanning Electron Microscopy (SEM)
85(2)
4.2.6 X-Ray Fluorescence (XRF) Spectroscopy
87(1)
4.2.7 Fourier Transform Infrared (FTIR) Spectroscopy
87(1)
4.2.8 Energy Dispersive Spectroscopy (EDS)
87(1)
4.2.9 Temperature Cycling
88(2)
4.2.10 Hermetic Seal Test
90(1)
4.3 Limitations and Challenges
90(1)
4.4 Summary
91(1)
References
92(3)
5 Electrical Tests for Counterfeit Detection 95(14)
5.1 Test Equipment
96(1)
5.1.1 Bench Equipment
96(1)
5.1.2 Automatic Test Equipment (ATE)
97(1)
5.2 Curve Tracing
97(2)
5.3 Key Electrical Parameters Testing
99(4)
5.4 Burn-in Testing
103(1)
5.5 Limitations and Challenges
103(2)
5.6 Summary
105(1)
References
106(3)
6 Counterfeit Test Coverage: An Assessment of Current Counterfeit Detection Methods 109(24)
6.1 Disparity in Capabilities and Expertise Among Test Labs
110(1)
6.2 Terminologies
111(4)
6.2.1 Tier Level
111(1)
6.2.2 Target Confidence
112(1)
6.2.3 Test Methods
112(1)
6.2.4 Counterfeit Defects
112(1)
6.2.5 Confidence Level Matrix
112(1)
6.2.6 Defect Frequency
113(1)
6.2.7 Decision Index
113(1)
6.2.8 Defect Mapping Matrix
113(2)
6.2.9 Challenges Associated with Input Acquisition
115(1)
6.3 Test Metrics
115(2)
6.3.1 Counterfeit Defect Coverage (CDC)
115(1)
6.3.2 Counterfeit Type Coverage (CTC)
116(1)
6.3.3 Not-Covered Defects (NCDs)
117(1)
6.3.4 Under-Covered Defects (UCDs)
117(1)
6.4 Assessment Framework
117(13)
6.4.1 Static Assessment
118(4)
6.4.2 Dynamic Assessment
122(4)
6.4.3 Comparison Between Static Assessment and Dynamic Assessment
126(4)
6.5 Summary
130(1)
References
130(3)
7 Advanced Detection: Physical Tests 133(24)
7.1 Limitation in 2D Characterization
134(3)
7.2 Four Dimensional Scanning Electron Microscopy
137(8)
7.2.1 Acquisition Stage
138(4)
7.2.2 Depth Extraction Stage
142(3)
7.3 Quantification of a 3D Surface: Improper Texture Variations
145(2)
7.4 3D X-Ray Microscopy
147(4)
7.5 Results Summary
151(1)
7.6 Summary
152(1)
References
153(4)
8 Advanced Detection: Electrical Tests 157(18)
8.1 Two Phase Detection Approach for Recycled FPGAs
158(9)
8.1.1 Aging and Recycled FPGAs
158(3)
8.1.2 Two Phase Recycled FPGA Detection
161(6)
8.2 Path-Delay Analysis
167(5)
8.2.1 Impact of Aging on Path Delays
168(1)
8.2.2 Path Delay Fingerprinting
168(2)
8.2.3 Clock Sweeping
170(1)
8.2.4 Data Analysis
171(1)
8.2.5 Results
171(1)
8.3 Early Failure Rate (EFR) Analysis
172(1)
8.4 Summary
172(1)
References
173(2)
9 Combating Die and IC Recycling 175(28)
9.1 RO-Based CDIR Sensor
178(11)
9.1.1 Simple RO-CDIR
178(1)
9.1.2 Limitations of Simple RO-CDIR
179(2)
9.1.3 Design and Operation of NBTI-Aware RO-CDIR
181(1)
9.1.4 Overhead Analysis
182(1)
9.1.5 Simulation of the NBTI-Aware RO-CDIR
183(2)
9.1.6 Misprediction Rate Analysis
185(3)
9.1.7 Workload Analysis
188(1)
9.1.8 Attack Analysis
188(1)
9.2 Antifuse-Based CDIR Structures
189(6)
9.2.1 Antifuse Memory
189(1)
9.2.2 Clock AF-Based (CAF-Based) CDIR
190(3)
9.2.3 Signal AF-Based (SAF-Based) CDIR
193(1)
9.2.4 Area Overhead Analysis
194(1)
9.2.5 Attack Analysis
195(1)
9.3 Fuse-Based CDIR
195(4)
9.3.1 Area Overhead Analysis
198(1)
9.3.2 Attack Analysis
198(1)
9.4 Summary
199(1)
References
199(4)
10 Hardware IP Watermarking 203(20)
10.1 Intellectual Property (IP)
204(1)
10.2 IP Reuse and IP Piracy
205(1)
10.3 Approaches to Secure IP
206(1)
10.4 Hardware Watermarking
207(13)
10.4.1 Constraint-Based Watermarking
209(4)
10.4.2 Additive Watermarking
213(2)
10.4.3 Module-Based Watermarking
215(3)
10.4.4 Power-Based Watermarking
218(2)
10.5 Summary
220(1)
References
221(2)
11 Prevention of Unlicensed and Rejected ICs from Untrusted Foundry and Assembly 223(20)
11.1 Fabless Business Model
224(1)
11.2 Fabless Supply Chain Vulnerabilities
225(1)
11.3 Background
226(1)
11.3.1 Related Work
226(1)
11.3.2 Challenges
226(1)
11.4 Connecticut Secure Split-Test
227(11)
11.4.1 Overview
227(2)
11.4.2 CSST Structure
229(4)
11.4.3 Experimental Results and Analysis of CSST
233(5)
11.5 Summary
238(2)
References
240(3)
12 Chip ID 243(22)
12.1 General Requirements of Chip ID
244(1)
12.2 Die ID
245(8)
12.2.1 Physically Unclonable Functions (PUFs)
245(1)
12.2.2 PUF Structures
246(4)
12.2.3 PUF Quality and Metrics
250(1)
12.2.4 PUF Applications in Hardware Security
251(1)
12.2.5 Challenges and Limitations
251(2)
12.3 Package ID
253(7)
12.3.1 Encrypted QR Codes
253(1)
12.3.2 DNA Markings
254(2)
12.3.3 Nanorods
256(1)
12.3.4 Capacitive (Coating) Physical Unclonable Functions
256(2)
12.3.5 Challenges and Limitations
258(2)
12.4 Limitations of Chip IDs for Different Counterfeit Types
260(1)
12.5 Summary
261(1)
References
262(3)
Index 265
Mark (Mohammad) Tehranipoor is currently the Charles H. Knapp Associate Professor of Electrical and Computer Engineering Department at the University of Connecticut.

His current research projects include: computer-aided design and test for CMOS VLSI designs, hardware security and trust, counterfeit IC detection and prevention, and reliable systems design at nanoscale. Prof. Tehranipoor has published over 200 journal articles and refereed conference papers and has given more than 125 invited talks and keynote addresses since 2006. In addition, he has published five books and ten book chapters. His projects are sponsored by both the industry (SRC, Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Cisco, Qualcomm, MediaTeck, etc.) and Government (NSF, ARO, MDA, DOD, DOE, etc.).

He is a recipient of several best paper awards, the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2010 IEEE CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2009 NSF CAREER Award, the 2009 UConn ECE Research Excellence Award, and the 2012 UConn SOE Outstanding Faculty Advisor Award.

He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, and IEEE Computer Society Computing Now. He served as Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011.

He co-founded a new symposium called IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) ()http://www.engr.uconn.edu/HOST/) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair of Steering Committee for HOST. He is also a co-founder of Trust-Hub (www.trust-hub.org). He is currently serving as the Associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers, an Associate Editor for JETTA, an Associate Editor for Journal of Low Power Electronics (JOLPE), an Associate Editor for ACM Transactions for Design Automation of Electronic Systems (TODAES), an IEEE Distinguished Speaker, and an ACM Distinguished Speaker.

Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA.