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El. knyga: ESD Handbook

Steven H. Voldman (IBM, USA)

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Other digital carrier (Kaina: 199,61 €) - 26-Mar-2021

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Išleidimo metai: 02-Mar-2021
Leidėjas: John Wiley & Sons Inc
Kalba: eng
ISBN-13: 9781119233107

Kitos knygos pagal šią temą:

Electricity, electromagnetism & magnetism

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Bibliotekoms

Formatas: PDF+DRM
Išleidimo metai: 02-Mar-2021
Leidėjas: John Wiley & Sons Inc
Kalba: eng
ISBN-13: 9781119233107

Kitos knygos pagal šią temą:

Electricity, electromagnetism & magnetism

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A practical and comprehensive reference that explores Electrostatic Discharge (ESD) in semiconductor components and electronic systems 

The ESD Handbook offers a comprehensive reference that explores topics relevant to ESD design in semiconductor components and explores ESD in various systems. Electrostatic discharge is a common problem in the semiconductor environment and this reference fills a gap in the literature by discussing ESD protection. Written by a noted expert on the topic, the text offers a topic-by-topic reference that includes illustrative figures, discussions, and drawings.

The handbook covers a wide-range of topics including ESD in manufacturing (garments, wrist straps, and shoes); ESD Testing; ESD device physics; ESD semiconductor process effects; ESD failure mechanisms; ESD circuits in different technologies (CMOS, Bipolar, etc.); ESD circuit types (Pin, Power, Pin-to-Pin, etc.); and much more. In addition, the text includes a glossary, index, tables, illustrations, and a variety of case studies.

Contains a well-organized reference that provides a quick review on a range of ESD topics
Fills the gap in the current literature by providing information from purely scientific and physical aspects to practical applications
Offers information in clear and accessible terms
Written by the accomplished author of the popular ESD book series

Written for technicians, operators, engineers, circuit designers, and failure analysis engineers, The ESD Handbook contains an accessible reference to ESD design and ESD systems. 

About the Author

xxxvii

Acknowledgements

xxxix

1 ESD, EOS, EMI, EMC, and Latchup

(20)

1.1 Electrostatic Discharge (ESD)

(1)

1.1.1 What Do You Mean by the Term "Electrostatic Discharge"?

(1)

1.2 Human Body Model (HBM)

(1)

1.2.1 Why Do We Have a Human Body Model?

(1)

1.2.1.1 What Does it Characterize?

(1)

1.3 Machine Model (MM)

(1)

1.3.1 What is the Purpose of the Machine Model?

(1)

1.3.1.1 How is it Different from the Human Body Model?

(1)

1.4 Cassette Model

(1)

1.4.1 Why Do We Have a Cassette Model? What Does it Represent?

(1)

1.5 Charged Device Model (CDM)

(1)

1.5.1 What is the Charged Device Model?

(1)

1.5.1.1 Why is it Important?

(1)

1.6 Transmission Line Pulse (TLP)

(3)

1.6.1 Why was the TLP Model Introduced?

(3)

1.6.1.1 Why is it So Valuable for Circuit Designers and ESD Engineers?

(3)

1.7 Very Fast Transmission Line Pulse (VF-TLP)

(1)

1.7.1 Why Do We Need to Evaluate VF-TLP?

(1)

1.8 Electrical Overstress (EOS)

(1)

1.9 Electrical Overstress (EOS)

(1)

1.9.1 How is EOS Differ from ESD?

(1)

1.10 EOS Sources - Lightning

(1)

1.11 EOS Sources - Electromagnetic Pulse (EMP)

(1)

1.12 EOS Sources - Machinery

(1)

1.13 EOS Sources - Power Distribution

(1)

1.14 EOS Sources - Switches, Relays, and Coils

(1)

1.15 EOS Design Flow and Product Definition

(1)

1.15.1 How Do You Add EOS to the Product Design Flow?

(1)

1.16 EOS Sources - Design Issues

(1)

1.17 Electromagnetic Interference (EMI)

(1)

1.17.1 What Type of Products are Sensitive to EMI?

(1)

1.18 Electromagnetic Compatibility (EMC)

(1)

1.19 Latchup

(1)

1.19.1 What is Latchup? Why is it Important?

(1)

Questions and Answers

(1)

1.20 Summary and Closing Comments

(1)

References

(6)

2 ESD in Manufacturing

(34)

2.1 Flooring

(1)

2.1.1 Question: Why is Flooring an ESD Issue?

(1)

2.2 Work Surfaces

(1)

2.2.1 Why are Worksurfaces an ESD Issue?

(1)

2.3 Garments

(1)

2.3.1 Question: Do Garments Play a Role in Charging of Products?

(1)

2.4 Wrist Straps

(1)

2.4.1 Why are Wrist Straps Required in a Manufacturing Environment?

(1)

2.5 Shoes - Footwear

(1)

2.5.1 How Do Shoes Influence Tribocharging?

(1)

2.6 Ionization

(1)

2.6.1 What is the Role of Ionization in Manufacturing?

(1)

2.7 Clean Rooms

(2)

2.7.1 Seating

(2)

2.7.1.1 Why are Chairs a Charging Issue?

(2)

2.8 Carts

(1)

2.8.1 Why are Carts an ESD Issue?

(1)

2.9 Shipping Tubes

(1)

2.9.1 Why are Shipping Tubes a Problem?

(1)

2.10 Trays

(1)

2.10.1 What Application are Sensitive to ESD in Trays?

(1)

2.11 Measurements

(1)

2.11.1 Packaging and Shipping

(1)

2.11.2 ESD Identification

(1)

2.12 Verification

(1)

2.12.1 ESD Program Management - Twelve Steps to Building an ESD Strategy

(1)

2.13 Audit

(1)

2.13.1 ESD Program Auditing

(1)

2.14 Triboelectric Charging - How Does it Happen?

(1)

2.15 Conductors, Semiconductors, and Insulators

(1)

2.16 Static Dissipative Materials

(1)

2.17 ESD and Materials

(1)

2.18 Electrification and Coulomb's Law

(2)

2.18.1 Electrification by Friction

(1)

2.18.2 Electrification by Induction

(1)

2.18.3 Electrification by Conduction

(1)

2.19 Electromagnetism and Electrodynamics

(1)

2.20 Electrical Breakdown

(3)

2.20.1 Electrostatic Discharge and Breakdown

(1)

2.20.2 Breakdown and Paschen's Law

(1)

2.20.3 Breakdown and Townsend

(1)

2.20.4 Breakdown and Toepler's Law

(1)

2.20.5 Avalanche Breakdown

(1)

2.21 Electro-Quasistatics and Magnetoquasistatics

(1)

2.22 Electrodynamics and Maxwell's Equations

(1)

2.23 Electrostatic Discharge (ESD)

(1)

2.24 Electromagnetic Compatibility (EMC)

(1)

2.25 Electromagnetic Interference (EMI)

(1)

2.26 Fundamentals of Manufacturing and Electrostatics

(1)

2.27 Materials, Tooling, Human Factors, and Electrostatic Discharge

(1)

2.28 Materials and Human-induced Electric Fields

(1)

2.29 Manufacturing Environment and Tooling

(1)

2.30 Manufacturing Equipment and ESD Manufacturing Problems

(1)

2.31 Manufacturing Materials

(1)

2.32 Measurement and Test Equipment

(1)

2.33 Manufacturing Testing for Compliance

(1)

2.34 Grounding and Bonding Systems

(1)

2.35 Work Surfaces

(1)

2.36 Wrist Straps

(1)

2.37 Constant Monitors

(1)

2.38 Footwear

(1)

2.39 Floors

(1)

2.40 Personnel Grounding with Garments

(1)

2.41 Garments

(1)

2.42 Air Ionization

(1)

2.43 Seating

(1)

2.44 Packaging and Shipping

(1)

2.45 Trays

(1)

2.46 ESD Identification

(1)

2.47 ESD Program Auditing

(1)

2.48 ESD On-Chip Protection

(1)

2.49 ESD, EOS, EMI, EMC, and Latchup

(1)

2.49.1 ESD

(1)

2.49.2 EOS

(1)

2.49.3 EMI

(1)

2.49.4 EMC

(1)

2.50 Manufacturing Electrical Overstress (EOS)

(2)

2.50.1 Manufacturing EOS Sources - Machinery

(1)

2.50.2 Manufacturing EOS Sources - Power Distribution

(1)

2.50.3 Manufacturing EOS Sources - Switches, Relays and Coils

(1)

2.51 EMI

(1)

2.52 EMC

(1)

2.53 Summary and Closing Comments

(1)

References

(5)

3 ESD Standards

(10)

3.1 Factory - Flooring

(1)

3.1.1 Factory - Worksurfaces

(1)

3.1.2 Factory - Ionization

(1)

3.1.3 Factory - Garments

(1)

3.1.4 Factory - Wrist Straps

(1)

3.1.5 Factory - Grounding

(1)

3.2 Factory - Resistance Measurement of Materials

(2)

3.2.1 Components - HBM

(1)

3.2.2 Components - MM

(1)

3.2.3 Components - CDM

(1)

3.2.4 Components - SDM

(1)

3.2.5 Components - TLP

(1)

3.2.6 Components - VF-TLP

(1)

3.2.7 Systems - IEC 61000-4-2

(1)

3.2.8 Systems - Cable Discharge Event (CDE)

(1)

3.2.9 Components - HMM

(1)

3.3 JEDEC

(1)

3.4 International Electro-Technical Commission (IEC)

(1)

3.5 IEEE

(1)

3.6 Department of Defense (DOD)

(1)

3.7 Military Standards

(1)

3.8 SAE

(1)

3.9 Summary and Closing Comments

(1)

Questions and Answers

(1)

References

(4)

4 ESD Testing

(52)

4.1 Electrostatic Discharge (ESD) Testing

(1)

4.2 ESD Models

(4)

4.2.1 Human Body Model (HBM)

(1)

4.2.2 HBM Pulse Waveform

(1)

4.2.3 HBM Equivalent Circuit Model

(1)

4.2.4 HBM Tester Source

(2)

4.3 HBM Test System

(1)

4.4 HBM Two-pin Test System

(1)

4.5 Machine Model (MM)

(1)

4.5.1 MM Equivalent Circuit

(1)

4.5.2 MM Pulse Waveform

(1)

4.5.3 ESD MM Tester Source

(1)

4.6 Small Charge Model (SCM)

(1)

4.7 Small Charge Model Source

(1)

4.7.1 Charged Device Model

(1)

4.8 CDM Pulse Waveform

(5)

4.8.1 CDM Commercial Tester

(1)

4.8.2 CDM Equivalent Circuit

(2)

4.8.3 CDM Equivalent Circuit with Tester Chassis

(1)

4.8.4 Human Metal Model (HMM)

(1)

4.8.5 HMM Pulse Waveform

(1)

4.8.6 HMM Pulse Waveform Equation

(1)

4.9 HMM Equivalent Circuit

(1)

4.10 HMM Test Equipment

(1)

4.11 HMM Test Configuration

(1)

4.11.1 HMM Horizontal Configuration

(1)

4.11.2 HMM Vertical Configuration

(1)

4.12 HMM Fixture Board

(4)

4.13 Transmission Line Pulse (TLP)

(2)

4.14 TLP Test Systems

(3)

4.14.1 Very Fast Transmission Line Pulse (VF-TLP)

(1)

4.14.2 VF-TLP Pulse Waveform

(3)

4.15 IEC 61000-4-2

(2)

4.15.1 IEC 61000-4-2 Air Discharge

(1)

4.15.2 IEC 61000-4-2 Direct Contact Discharge

(1)

4.15.3 IEC 61000-4-2 Pulse Waveform

(1)

4.15.4 IEC 61000-4-2 Pulse Waveform Equation

(1)

4.16 Equivalent Circuit

(1)

4.17 Test Equipment

(1)

4.18 Cable Discharge Event (CDE)

(3)

4.18.1 CDE - Charging, Discharging, and Pulse Waveform

(1)

4.18.2 Charging Process

(1)

4.18.3 Discharging Process

(1)

4.19 CDE Pulse Waveform

(1)

4.20 Equivalent Circuit

(1)

4.21 Commercial Test Systems

(1)

4.22 Systems Electromagnetic Interference (EMI)

(1)

4.23 Electromagnetic Compatibility (EMC)

(1)

4.24 Electrical Overstress (EOS)

(1)

4.25 Latchup

(1)

4.26 Electrical Overstress (EOS)

(1)

4.27 EOS Sources - Lightning

(1)

4.28 EOS Sources - Electromagnetic Pulse (EMP)

(1)

4.29 Electromagnetic Compatibility

(3)

4.30 Summary and Closing Comments

100

(1)

References

100

(17)

5 BD Device Physics

117

(72)

5.1 Electro-thermal Instability

117

(1)

5.2 Stable System

118

(1)

5.3 Unstable System

118

(2)

5.4 Differential Relation of Voltage and Current

120

(1)

5.5 Time Constant Hierarchy

121

(1)

5.6 Thermal Physics Time Constants

121

(1)

5.7 Adiabatic, Thermal Diffusion Time Scale and Steady State

121

(1)

5.8 Electro-quasistatic and Magnetoquasistatics

122

(2)

5.9 Electrical Instability

124

(1)

5.9.1 Thermal Time Constant Approach

124

(2)

5.9.1.1 Heat Capacity

124

(1)

5.9.1.2 Thermal Diffusion

124

(1)

5.9.1.3 Heat Transport Equation

124

(1)

5.10 Thermal Physics Time Constants

125

(1)

5.11 Adiabatic, Thermal Diffusion Time Scale and Steady State

126

(1)

5.12 Electrical Instability and Breakdown

126

(1)

5.12.1 Electrical Instability

126

(1)

5.13 Spatial Instability and Electro-thermal Current Constriction

127

(1)

5.14 Equipotential Surface

127

(1)

5.15 Heat Flow

128

(1)

5.16 Conservation of Heat

128

(1)

5.17 Electric Potential and Temperature Gradient

128

(1)

5.17.1 Maximum Temperature and Minimum Potential

128

(1)

5.18 Electric Energy, Resistivity, and Thermal Conductivity

129

(2)

5.18.1 Intrinsic Temperature

129

(1)

5.18.2 Radius of Current Constriction

130

(1)

5.18.3 Differential Potential and Differential Thermal Potential

130

(1)

5.18.4 Resistance Reduction and Current Constriction

130

(1)

5.18.5 Contact Radius and Contour Relationship

131

(1)

5.18.6 Current Constriction Relationship

131

(1)

5.18.7 Intrinsic Temperature

131

(1)

5.19 Breakdown

131

(5)

5.19.1 Paschen's Breakdown Theory

131

(1)

5.19.2 Townsend's Concept

132

(1)

5.19.3 Toepler's Law

132

(1)

5.19.4 Avalanche Breakdown

133

(2)

5.19.4.1 Energy Transfer from Electric Field to Carriers

133

(1)

5.19.4.2 Energy Balance Relationship

133

(1)

5.19.4.3 Impact Ionization Coefficient

133

(1)

5.19.4.4 Impact Ionization Mean Free Path and Optical Generation Mean Free Path

134

(1)

5.19.4.5 Impact Ionization Coefficient

134

(1)

5.19.5 Breakdown in Air

135

(1)

5.20 Electron Current Continuity Relationship

136

(2)

5.20.1 Time-dependent Electron Population

136

(1)

5.20.2 Electron Density

137

(1)

5.21 Air Breakdown and Peak Currents

138

(1)

5.22 Electro-thermal Instability

139

(2)

5.23 Mathematical Methods - Green's Function and Method of Images

141

(2)

5.23.1 Case of a Parallelepiped in an Infinite Medium

142

(1)

5.24 Mathematical Methods - Green's Function and Method of Images

143

(5)

5.24.1 Case of a Parallelepiped in an Infinite Medium

144

(1)

5.24.2 Case of the Semi-infinite Domain

145

(3)

5.25 Mathematical Methods - Integral Transforms of the Heat Conduction Equation

148

(4)

5.26 Flux Potential Transfer Relations Matrix Methodology

152

(2)

5.27 Heat Equation Variable Conductivity

154

(2)

5.28 Mathematical Methods - Boltzmann Transformation

156

(2)

5.29 Mathematical Methods - The Duhamel Formulation

158

(2)

5.30 Spherical Source Tasca Model

160

(3)

5.31 Wunsch-Bell Model

163

(3)

5.32 The Smith and Littau Model

166

(2)

5.33 The Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Model

168

(1)

5.34 The Vlasov-Sinkevitch Model

169

(1)

5.35 The Dwyer, Franklin and Campbell Model

169

(5)

5.36 Negative Differential Resistor and Resistor Ballasting

174

(2)

5.37 Ash Model - Nonlinear Failure Power Thresholds

176

(2)

5.38 Statistical Models for ESD Prediction

178

(2)

5.39 Summary and Closing Comments

180

(1)

References

180

(9)

6 ESD Events and Protection Circuits

189

(46)

6.1 Human Body Model (HBM)

189

(2)

6.1.1 HBM Pulse Waveform

189

(1)

6.1.2 HBM Equivalent Circuit Model

189

(1)

6.1.3 HBM Tester Source

189

(1)

6.1.4 HBM Failure

190

(1)

6.2 Machine Model (MM)

191

(2)

6.2.1 MM Equivalent Circuit

191

(1)

6.2.2 MM Pulse Waveform

192

(1)

6.2.3 ESD MM Tester Source

192

(1)

6.2.4 Machine Model Example of MM Failure

193

(1)

6.3 Charged Device Model

193

(4)

6.3.1 CDM Pulse Waveform

193

(1)

6.3.2 CDM Commercial Tester

193

(3)

6.3.3 CDM Equivalent Circuit

196

(1)

6.3.4 CDM Equivalent Circuit with Tester Chassis

196

(1)

6.3.5 CDM Failure Mechanism

196

(1)

6.4 Human Metal Model (HMM)

197

(7)

6.4.1 HMM Pulse Waveform

198

(1)

6.4.2 HMM Pulse Waveform Equation

198

(2)

6.4.3 Equivalent Circuit

200

(1)

6.4.4 HMM Test Equipment

200

(1)

6.4.5 HMM Test Configuration

201

(1)

6.4.5.1 Horizontal Configuration

201

(1)

6.4.5.2 Vertical Configuration

202

(1)

6.4.6 HMM Fixture Board

202

(2)

6.5 IEC 61000-4-2 History

204

(5)

6.5.1 IEC 61000-4-2 Scope

204

(1)

6.5.2 IEC 61000-4-2 Purpose

204

(3)

6.5.2.1 Air Discharge

205

(1)

6.5.2.2 Direct Contact Discharge

205

(1)

6.5.2.3 Pulse Waveform

205

(1)

6.5.2.4 Pulse Waveform Equation

206

(1)

6.5.3 Equivalent Circuit

207

(1)

6.5.4 Test Equipment

207

(1)

6.5.5 Test Configuration

208

(1)

6.5.6 IEC 61000-4-2 ESD Protection Circuitry

208

(1)

6.5.7 ESD Guns

209

(1)

6.6 IEC 61000-4-5

209

(4)

6.6.1 History

209

(1)

6.6.2 IEC 61000-4-5 Scope

210

(1)

6.6.3 IEC 61000-4-5 Purpose

210

(1)

6.6.4 IEC 61000-4-5 Pulse Waveform

210

(1)

6.6.5 IEC 61000-4-5 Test Equipment

211

(1)

6.6.6 IEC 61000-4-5 Test Sequence and Procedure

212

(1)

6.6.7 Failure Mechanisms

213

(1)

6.6.8 IEC 61000-4-5 ESD Current Paths

213

(1)

6.6.9 ESD Protection Circuit Solutions

213

(1)

6.7 Cable Discharge Event (CDE)

213

(2)

6.7.1 Cable Discharge Event History

213

(2)

6.8 CDM Scope

215

(4)

6.8.1 CDM Purpose

215

(1)

6.8.2 Cable Discharge Event - Charging, Discharging, and Pulse Waveform

216

(1)

6.8.3 CDE Charging Process

216

(1)

6.8.4 CDE Discharging Process

217

(1)

6.8.5 CDE Pulse Waveform

217

(1)

6.8.6 CDE Equivalent Circuit

217

(1)

6.8.7 CDE Test Equipment

218

(24)

6.8.7.1 Commercial Test Systems

218

(1)

References

219

(16)

7 ESD Failure Mechanism

235

(46)

7.1 Tables of CMOS ESD Failure Mechanisms

235

(1)

7.2 LOCOS Isolation-Defined CMOS

235

(6)

7.3 LOCOS-bound Thick Oxide MOSFET

241

(1)

7.4 LOCOS-Bound Structures

242

(3)

7.4.1 LOCOS-bound P+/N-well Junction Diode

242

(2)

7.4.2 LOCOS-bound N+/P- Substrate Junction Diode

244

(1)

7.4.3 LOCOS-bound N-Well/P- Substrate Junction Diode

244

(1)

7.4.4 LOCOS-bound Lateral N-well to N-well

244

(1)

7.4.5 LOCOS-bound lateral N+ to N-well

245

(1)

7.5 Shallow Trench Isolation (STI)

245

(1)

7.6 STI Pull-down ESD Failure Mechanism

245

(1)

7.7 STI Pull-Down and Gate Wrap-Around

246

(1)

7.7.1 Silicide and Diodes

247

(1)

7.7.2 Non-silicided Diode Structures

247

(1)

7.8 MOSFETs

247

(5)

7.8.1 N-channel MOSFET

247

(3)

7.8.2 N-channel Multi-finger MOSFET

250

(2)

7.9 LOCOS-bound Thick Oxide MOSFET

252

(2)

7.9.1 Cascode Series N-channel MOSFET

252

(1)

7.9.2 P-channel MOSFET

252

(1)

7.9.3 P-channel Multi-finger MOSFET

253

(1)

7.9.4 Tungsten Silicide Gate MOSFET

253

(1)

7.9.5 Polysilicon Silicide Gate MOSFET

254

(1)

7.9.6 Metal Gate/High K Dielectric MOSFET

254

(1)

7.10 Bipolar Transistor Devices

254

(5)

7.10.1 LOCOS-bound Lateral PNP Bipolar

254

(1)

7.10.2 Polysilicon-defined Devices

254

(1)

7.10.3 Polysilicon-bound Gated Diode

255

(1)

7.10.4 Lateral Diode with Block Mask

255

(1)

7.10.5 Resistors

256

(1)

7.10.6 Diffused Resistors

256

(1)

7.10.7 N-well Resistors

256

(2)

7.10.8 Buried Resistors

258

(1)

7.11 Silicide Blocked N-diffusion Resistors

259

(1)

7.12 Silicon Germanium ESD Failure Mechanisms

259

(1)

7.13 Silicon Germanium Carbon ESD Failure Mechanisms

259

(1)

7.14 Gallium Arsenide Technology ESD Failure Mechanisms

260

(1)

7.15 Indium Gallium Arsenide ESD Failure Mechanisms

261

(2)

7.15.1 Magnetic Recording

261

(1)

7.15.2 FinFET Transistors

262

(1)

7.16 Micro Electromechanical (MEM) Systems

263

(2)

7.17 Micro-mirror Array Failures

265

(4)

7.17.1 Manufacturing Failure

265

(1)

7.17.2 EOS Failure Mechanisms

265

(2)

7.17.3 EOS Failure Mechanisms - Semiconductor Process - Application Mismatch

267

(1)

7.17.4 EOS Failure Mechanisms - Bond Wire Failures

267

(1)

7.17.5 EOS Failure Mechanisms - External Load to Chip Failures

268

(1)

7.17.6 EOS Failure Mechanisms - Printed Circuit Board (PCB) to Chip Failures

268

(1)

7.17.7 EOS Failure Mechanisms - Reverse Insertion

268

(1)

7.18 EOS Bond Pad and Interconnect Failure

269

(3)

7.18.1 EOS Failure - Packaging Failure

269

(1)

7.18.1.1 Electrical Overstress - Packaging Ablation

269

(3)

7.19 Summary and Closing Comments

272

(1)

References

273

(8)

8 ESD Design Synthesis

281

(82)

8.1 ESD Design Synthesis and Architecture Flow

281

(6)

8.1.1 Fundamental Concepts of ESD Design

281

(4)

8.1.2 Top-down ESD Design

285

(1)

8.1.3 Bottom-up ESD Design

285

(1)

8.1.4 Top-down ESD Design - Memory Semiconductor Chips

285

(1)

8.1.5 Top-down ESD Design - ASIC Design System

286

(1)

8.2 ESD Design - the Signal Path and the Alternate Current Path

287

(2)

8.3 ESD Electrical Circuit and Schematic Architecture Concepts

289

(1)

8.4 The Ideal ESD Network

289

(4)

8.4.1 Ideal ESD Networks and the Current-Voltage D.C. Design Window

289

(1)

8.4.2 The ESD Design Window

290

(1)

8.4.3 The Ideal ESD Networks in the Frequency Domain Design Window

291

(2)

8.5 Mapping Semiconductor Chips and ESD Designs

293

(1)

8.6 Mapping across Semiconductor Fabricators

294

(1)

8.7 ESD Design Mapping across Technology Generations

295

(11)

8.7.1 Mapping from Bipolar Technology to CMOS Technology

296

(1)

8.7.2 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology

297

(1)

8.7.3 Mapping from Bulk CMOS Technology to Silicon On Insulator (SOI)

297

(1)

8.7.4 ESD Design - Mapping CMOS to RF CMOS Technology

298

(8)

8.7.4.1 ESD Chip Architecture, and ESD Test Standards

299

(1)

8.7.4.2 ESD Chip Architecture, and ESD Testing

299

(1)

8.7.4.3 ESD Chip Architecture, and ESD Alternative Current Paths

300

(1)

8.7.4.4 ESD Circuits, I/O, and Cores

300

(1)

8.7.4.5 ESD Signal Pin Circuits

300

(2)

8.7.4.6 ESD Power Clamp Networks

302

(1)

8.7.4.7 ESD Rail-to-Rail Circuits

303

(1)

8.7.4.8 ESD Design and Noise

304

(1)

8.7.4.9 ESD Internal Signal Path ESD Networks

305

(1)

8.7.5 Cross Domain ESD Networks

306

(1)

8.8 ESD Networks, Sequencing, and Chip Architecture

306

(8)

8.8.1 ESD Design Synthesis - Latchup-free ESD Networks

307

(7)

8.8.1.1 ESD Design Concepts - Buffering - Inter-device

309

(1)

8.8.1.2 ESD Design Concepts - Ballasting - Inter-Device

309

(2)

8.8.1.3 ESD Design Concepts - Ballasting - Intra-device

311

(1)

8.8.1.4 ESD Design Concepts - Distributed Load Techniques

311

(1)

8.8.1.5 ESD Design Concepts - Dummy Circuits

312

(1)

8.8.1.6 ESD Design Concepts - Power Supply Decoupling

313

(1)

8.8.1.7 ESD Design Concepts - Feedback Loop Decoupling

313

(1)

8.9 ESD Layout and Floorplan-related Concepts

314

(9)

8.9.1 Design Symmetry

314

(1)

8.9.2 Design Segmentation

315

(8)

8.9.2.1 ESD Design Concepts - Utilization of Empty Space

317

(1)

8.9.2.2 ESD Design Synthesis - Across Chip Line Width Variation (ACLU)

317

(1)

8.9.2.3 ESD Design Concepts - Dummy Shapes

318

(1)

8.9.2.4 ESD Design Concepts - Dummy Masks

319

(1)

8.9.2.5 ESD Design Concepts - Adjacency

320

(1)

8.9.2.6 ESD Design Concepts - Analog Circuit Techniques

321

(1)

8.9.2.7 ESD Design Concepts - Wire Bonds

322

(1)

8.9.2.8 ESD Design Rules

322

(1)

8.9.2.9 ESD Design Rule Check (DRC)

322

(1)

8.9.2.10 ESD Layout Versus Schematic (LVS)

322

(1)

8.9.3 Electrical Resistance Checking (ERC)

323

(1)

8.10 ESD Architecture and Floor-planning

323

(24)

8.10.1 ESD Design Floorplan

323

(1)

8.10.2 Peripheral I/O Design

324

(3)

8.10.2.1 Pad Limited Peripheral I/O Design Architecture

324

(2)

8.10.2.2 Pad Limited Peripheral I/O Design Architecture - Staggered I/O

326

(1)

8.10.3 Core Limited Peripheral I/O Design Architecture

327

(1)

8.10.4 Lumped ESD Power Clamp in Peripheral I/O Design Architecture

328

(1)

8.10.5 Lumped ESD Power Clamps in Peripheral I/O Design Architecture in the Semiconductor Chip Corners

328

(1)

8.10.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Power Pads

328

(1)

8.10.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Master/Slave ESD Power Clamp System

329

(4)

8.10.7.1 Array I/O

330

(1)

8.10.7.2 Array I/O - Off Chip Driver (OCD) Banks

331

(1)

8.10.7.3 Array I/O Nibble Architecture

332

(1)

8.10.8 Array I/O Pair Architecture

333

(1)

8.10.9 Array I/O - Fully Distributed

334

(4)

8.10.10 ESD Architecture - Dummy Bus Architectures

338

(1)

8.10.11 ESD Architecture - Dummy VDD Bus

338

(1)

8.10.12 ESD Architecture - Dummy Ground (Vss) Bus

339

(50)

8.10.12.1 Native Voltage Power Supply Architecture

340

(1)

8.10.12.2 Single Power Supply Architecture

340

(1)

8.10.12.3 Mixed Voltage Architecture

340

(5)

8.10.12.4 Mixed Signal Architecture

345

(1)

8.10.12.5 Mixed-system Architecture - Digital and Analog CMOS

345

(2)

8.11 Digital and Analog CMOS Architecture

347

(1)

8.12 Digital and Analog Floorplan - Placement of Analog Circuits

348

(2)

8.13 Mixed-signal Architecture - Digital, Analog, and RF Architecture

350

(1)

8.14 Summary and Closing Comments

351

(1)

Questions

351

(1)

References

352

(11)

9 On-chip ESD Protection Circuits - Input Circuitry

363

(78)

9.1 Receivers and ESD

363

(1)

9.2 Receivers and Receiver Delay Time

363

(1)

9.3 ESD Loading Effect on Receiver Performance

364

(1)

9.4 Receivers and HBM

365

(1)

9.5 Receivers and CDM

366

(2)

9.6 Receivers and Receiver Evolution

368

(1)

9.7 Receiver Circuits with Half-pass Transmission Gate

368

(3)

9.8 Receiver with Full-pass Transmission Gate

371

(2)

9.9 Receiver, Half-pass Transmission Gate, and Keeper Network

373

(4)

9.10 Receiver, Half-pass Transmission Gate, and the Modified Keeper Network

377

(2)

9.11 Receiver Circuits with Pseudo-zero VT Half-pass Transmission Gates

379

(2)

9.12 Receiver with Zero VT Transmission Gate

381

(2)

9.13 Receiver Circuits with Bleed Transistors

383

(1)

9.14 Receiver Circuits with Test Functions

384

(1)

9.15 Receiver with Schmitt Trigger Feedback Network

385

(4)

9.16 Bipolar Transistor Receivers

389

(8)

9.16.1 Bipolar Single-ended Receiver Circuits

389

(1)

9.16.2 Differential Receivers

390

(1)

9.16.3 Signal Differential Receiver

391

(1)

9.16.4 Signal CMOS Differential Receivers

391

(1)

9.16.5 Signal Bipolar Differential Receivers

391

(6)

9.17 CMOS Differential Receiver with Analog Layout Concepts

397

(1)

9.18 CMOS Differential Receiver Capacitance Loading

398

(1)

9.19 CMOS Differential Receiver ESD Mismatch

398

(2)

9.20 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout

400

(3)

9.21 Analog Differential Pair Common Centroid Design Layout - Signal-Pin to Signal-Pin and Parasitic ESD Elements

403

(2)

9.22 Off-chip Drivers (OCD)

405

(2)

9.23 Off-chip Driver I/O Standards and ESD

407

(1)

9.24 Off-chip Driver (OCD) ESD Design Basics

408

(6)

9.24.1 OCD: CMOS Asymmetric Pull-up/Pull-down

408

(2)

9.24.2 OCD: CMOS Symmetric Pull-up/Pull-down

410

(1)

9.24.3 OCD: Gunning Transceiver Logic (GTL)

411

(1)

9.24.4 OCD: High-speed Transceiver Logic (HSTL)

412

(1)

9.24.5 OCD: Stub Series Terminated Logic (SSTL)

413

(1)

9.25 Off-chip Drivers (OCD): Mixed Voltage Interface

414

(1)

9.26 Off-chip Drivers (OCD): Self-bias Well OCD Networks

414

(1)

9.27 Self-bias Well Off-chip Driver (OCD) Networks

415

(2)

9.28 ESD Protection Networks for Self-bias Well OCD Networks

417

(1)

9.29 Programmable Impedance Off-chip Driver (OCD) Network

418

(4)

9.30 ESD Input Protection Networks for Programmable Impedance Off-chip Drivers

422

(1)

9.31 Universal Off-chip Drivers

423

(1)

9.32 Gate Array Off-chip Driver Design

423

(2)

9.32.1 Gate Array Off-chip Driver ESD Design Practices

423

(1)

9.32.2 Gate Array OCD Design - Usage of Unused Elements

423

(2)

9.33 Gate Array OCD Design - Impedance Matching of Unused Elements

425

(1)

9.34 OCD ESD Design - Power Rails Over Multi-finger MOSFETs

426

(1)

9.35 Off-chip Driver: Gate-modulated MOSFET ESD Network

427

(1)

9.36 Off-chip Driver Simplified Gate Modulated Network

428

(1)

9.37 Off-chip Drivers ESD Design: Integration of Coupling and Ballasting Techniques

428

(1)

9.38 Ballasting and Coupling

429

(1)

9.39 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with Diode

429

(1)

9.40 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with a MOSFET

430

(1)

9.41 Gate-coupled Domino Resistor-ballasted MOSFET

431

(2)

9.42 Substrate-modulated Resistor Ballasted MOSFET

433

(1)

9.43 Summary and Closing Comments

434

(1)

Problems

435

(2)

References

437

(4)

10 On-Chip ESD Protection Circuits - ESD Power Clamps

441

(50)

10.1 ESD Power Clamps

441

(1)

10.2 ESD Power Clamp Design Practices

441

(1)

10.3 Current Loops

442

(1)

10.4 Impedance

442

(1)

10.5 Segmentation

443

(1)

10.6 Voltage Limitations

443

(1)

10.7 Latchup

443

(1)

10.8 ESD Power Clamp Circuits

444

(1)

10.9 Classification of ESD Power Clamps

444

(1)

10.10 Master-Slave ESD Power Clamps

445

(1)

10.11 Trigger Networks

445

(1)

10.12 ESD Power Clamp Characteristics and Issues

445

(1)

10.13 Design Synthesis of ESD Power Clamp - Key Design Parameters

446

(1)

10.14 Design Synthesis of ESD Power Clamps Trigger Networks

446

(1)

10.15 Transient Response Frequency Trigger Element and the ESD Frequency Window

446

(1)

10.16 ESD Power Clamp Frequency Design Window

447

(1)

10.17 Design Synthesis of ESD Power Clamp - Voltage Triggered ESD Trigger Elements

448

(1)

10.18 Design Synthesis of ESD Power Clamp - The ESD Power Clamp Shunting Element

449

(1)

10.19 ESD Power Clamp Trigger Condition vs. Shunt Failure

450

(1)

10.20 ESD Clamp Element - Width Scaling

450

(1)

10.21 ESD Clamp Element - On-resistance

450

(1)

10.22 ESD Clamp Element - Safe Operating Area (SOA)

451

(1)

10.23 ESD Power Clamp Issues

451

(1)

10.24 ESD Power Clamp Issues - Power-up and Power-down

451

(1)

10.25 ESD Power Clamp Issues - False Triggering

452

(1)

10.26 ESD Power Clamp Issues - Pre-charging

452

(1)

10.27 ESD Power Clamp Issues - Post-charging

452

(1)

10.28 ESD Power Clamp Design

453

(3)

10.28.1 Native Power Supply RC-Triggered MOSFET ESD Power Clamp

453

(1)

10.28.2 Non-Native Power Supply RC-triggered MOSFET ESD Power Clamp

453

(1)

10.28.3 ESD Power Clamp Networks with Improved Inverter Stage Feedback

454

(1)

10.28.4 CMOS RC-trigger Clamp with CMOS PFET Half-latch Keeper Feedback

454

(1)

10.28.5 CMOS RC-trigger Clamp with CMOS PFET Full-latch Keeper Feedback

454

(2)

10.29 ESD Power Clamp Design Synthesis - Forward Bias Triggered ESD Power Clamps

456

(3)

10.29.1 ESD Power Clamp Design Synthesis - IEC 61000-4-2 Responsive ESD Power Clamps

456

(1)

10.29.2 ESD Power Clamp Design Synthesis - Pre-charging and Post-charging Insensitive ESD Power Clamps

457

(1)

10.29.3 Master/Slave ESD Power Clamp Systems

457

(2)

10.30 Series Stacked RC-triggered ESD Power Clamps

459

(4)

10.30.1 ESD Power Clamps - Triple Well Series Diodes as Core Clamps

459

(4)

10.31 Triple Well Diode String ESD Power Clamp

463

(1)

10.31.1 Triple Well ESD Power Clamp Network with Independent N-Band Voltage Bias

463

(1)

10.32 Bipolar ESD Power Clamps

464

(5)

10.32.1 Bipolar Voltage-Triggered ESD Power Clamps

464

(1)

10.32.2 Bipolar ESD Power Clamp - Zener Breakdown Voltage-Triggered

465

(1)

10.32.3 Bipolar ESD Power Clamp - BVCEO Voltage Triggered ESD Power Clamp

466

(1)

10.32.4 The Johnson Limit Relationship

466

(3)

10.33 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps

469

(11)

10.33.1 Mixed Voltage Interface Forward-bias Voltage and BVCEO-Breakdown Synthesized Bipolar ESD Power Clamps

471

(5)

10.33.2 Ultra-low-voltage Forward-biased Voltage-trigger BiCMOS ESD Power Clamp

476

(4)

10.34 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance-triggered

480

(1)

10.35 Silicon Controlled Rectifier Power Clamps

481

(2)

10.35.1 ESD Silicon Controlled Rectifier (SCR) Circuits

481

(1)

10.35.2 Uni-Directional Silicon Controlled Rectifier (SCR)

481

(1)

10.35.3 Bi-directional Silicon Controlled Rectifier (SCR) ESD Power Clamps

482

(1)

10.35.4 Medium Level SCR (MLSCR) ESD Power Clamps

482

(1)

10.35.5 Low Voltage Triggered SCR (LVTSCR) ESD Power Clamps

483

(1)

Problems

483

(3)

References

486

(5)

11 ESD Architecture and Floor Planning

491

(60)

11.1 ESD Design Floor Plan

491

(1)

11.2 Peripheral I/O Design

492

(1)

11.3 Pad Limited Peripheral I/O Design Architecture

493

(1)

11.4 Pad Limited Peripheral I/O Design Architecture - Staggered I/O

493

(2)

11.5 Core Limited Peripheral I/O Design Architecture

495

(1)

11.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture

496

(1)

11.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners

496

(1)

11.8 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Power Pads

497

(1)

11.9 Lumped ESD Power Clamp in Peripheral I/O Design Architecture -Master/Slave ESD Power Clamp System

498

(1)

11.10 Array I/O

498

(3)

11.10.1 Array I/O - Off Chip Driver (OCD) Banks

499

(2)

11.11 Array I/O Nibble Architecture

501

(2)

11.12 Array I/O Pair Architecture

503

(1)

11.13 Array I/O - Fully Distributed

504

(3)

11.14 ESD Architecture - Dummy Bus Architecture

507

(1)

11.15 ESD Architecture - Dummy VDD Bus

507

(1)

11.16 ESD Architecture - Dummy Ground (VSS) Bus

508

(1)

11.17 Native Voltage Power Supply Architecture

508

(1)

11.18 Single Power Supply Architecture

509

(1)

11.19 Mixed Voltage Architecture

509

(1)

11.20 Mixed Voltage Architecture - Single Power Supply

509

(2)

11.21 Mixed Voltage Architecture - Dual Power Supply

511

(3)

11.22 Mixed Signal Architecture

514

(1)

11.22.1 Mixed Signal Architecture - CMOS

514

(1)

11.22.2 Mixed System Architecture - Digital and Analog CMOS

514

(1)

11.22.3 Digital and Analog CMOS Architecture

514

(1)

11.23 Digital and Analog Floor Plan - Placement of Analog Circuits

515

(3)

11.24 Mixed Signal Architecture - Digital, Analog, and RF Architecture

518

(1)

11.25 ESD Power Grid Design

519

(6)

11.25.1 ESD Power Grid

519

(1)

11.25.2 ESD Power Grid - Key ESD Design Parameters

519

(1)

11.25.3 Power Grid Layout Design

519

(1)

11.25.4 Power Grid Design - Slotting of Power Grid

519

(1)

11.25.5 Power Grid Design - Segmentation of Power Grids

520

(1)

11.25.6 Power Grid Design - Chip Corners

521

(1)

11.25.7 Power Grid Design - Stacking of Metal Levels

522

(1)

11.25.8 Power Grid Design - Wiring Bays and Weaved Power Bus Designs

523

(1)

11.25.9 ESD Specification Power Grid Considerations

523

(1)

11.25.10 CDM Specification Power Grid and Interconnect Design Considerations

523

(1)

11.25.11 HMM and IEC Specification Power Grid and Interconnect Design Considerations

524

(1)

11.25.12 Semiconductor Chip Guard Ring Seal

524

(1)

11.26 I/O to Core Guard Rings

525

(2)

11.26.1 I/O to I/O Guard Rings

526

(1)

11.27 Within I/O Guard Rings

527

(1)

11.27.1 Within I/O Cell Guard Ring

527

(1)

11.28 ESD-to-I/O Off-Chip Driver (OCD) Guard Ring

527

(12)

11.28.1 ESD Signal Pin Guard Rings

528

(1)

11.28.2 ESD Signal Pin Guard Rings and Dual-diode ESD Network

529

(2)

11.28.3 Mixed Signal Guard Rings - Digital to Analog

531

(1)

11.28.4 Mixed Voltage Guard Rings - High Voltage to Low Voltage

531

(1)

11.28.5 High Voltage Guard Rings

532

(1)

11.28.6 Passive and Active Guard Rings

533

(1)

11.28.7 Passive Guard Rings

534

(1)

11.28.8 Active Guard Rings

534

(1)

11.28.9 Trench Guard Rings

535

(1)

11.28.10 Through Silicon Via (TSV) Guard Rings

536

(1)

11.28.11 Guard Ring Design Rule Checking (DRC)

537

(1)

11.28.12 Internal Latchup and Guard Ring Design Rules

537

(1)

11.28.13 External Latchup Guard Ring Design Rules

538

(1)

11.29 Guard Rings and Computer Aided Design (CAD) Methods

539

(2)

11.29.1 Built-in Guard Rings

539

(1)

11.29.2 Guard Ring Parameterized Cells (Pcell)

539

(1)

11.29.3 Post-processing Methodology of Guard Ring Modification

540

(1)

11.30 Summary and Closing Comments

541

(1)

References

541

(10)

12 ESD Digital Design

551

(32)

12.1 Fundamental Concepts of ESD Design

551

(1)

12.2 Concepts of ESD Digital Design

551

(1)

12.3 Device Response to External Events

552

(1)

12.4 Alternative Current Loops

553

(1)

12.4.1 Switches

553

(1)

12.4.2 Decoupling of Current Paths

553

(1)

12.5 Decoupling of Feedback Loops

554

(1)

12.6 Decoupling of Power Rails

554

(1)

12.7 Local and Global Distribution

554

(1)

12.8 Usage of Parasitic Elements

555

(1)

12.8.1 Buffering

555

(1)

12.8.2 Ballasting

555

(1)

12.9 Unused Section of a Semiconductor Device, Circuit, or Chip Function

556

(1)

12.10 Unused Corners

556

(1)

12.11 Unused White Space

556

(1)

12.12 Impedance Matching Between Floating and Non-floating Networks

556

(1)

12.13 Unconnected Structures

557

(1)

12.13.1 Utilization of Dummy Structures and Dummy Circuits

557

(1)

12.13.2 Non-scalable Source Events

557

(1)

12.13.3 Area Efficiency

557

(1)

12.14 Symmetry

557

(1)

12.15 Design Synthesis

557

(2)

12.15.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection

557

(1)

12.15.2 Electrical and Spatial Connectivity

558

(1)

12.15.3 Electrical Connectivity

558

(1)

12.15.4 Thermal Connectivity

559

(1)

12.15.5 Spatial Connectivity

559

(1)

12.16 ESD, Latchup, and Noise

559

(15)

12.16.1 Noise

560

(1)

12.16.2 Latchup

561

(1)

12.16.3 Interface Circuits and ESD Elements

561

(3)

12.16.4 ESD Power Clamp Networks

564

(2)

12.16.5 Placement of ESD Power Clamps

566

(2)

12.16.6 ESD Rail-to-Rail Networks

568

(2)

12.16.7 Placement of ESD Rail-to-Rail Networks

570

(1)

12.16.8 Peripheral and Array I/O

570

(2)

12.16.9 Guard Rings

572

(1)

12.16.10 Pads, Floating Pads, and No Connect Pads

573

(1)

12.17 Structures Under Bond Pads

574

(1)

12.18 Summary and Closing Comments

575

(1)

References

576

(7)

13 ESD Analog Design

583

(46)

13.1 Analog Design: Local Matching

583

(1)

13.2 Analog Design: Global Matching

583

(1)

13.3 Symmetry

584

(1)

13.3.1 Layout Design Symmetry

584

(1)

13.4 Analog Design - Local Matching

584

(1)

13.5 Analog Design - Global Matching

584

(2)

13.5.1 Design Orientation

585

(1)

13.5.2 Symmetry and Matching

585

(1)

13.5.3 Layout Design Symmetry

585

(1)

13.5.4 Thermal Symmetry

585

(1)

13.6 Common Centroid Design

586

(1)

13.7 Common Centroid Arrays

586

(1)

13.7.1 One-axis Common Centroid Design

586

(1)

13.7.2 Two-axis Common Centroid Design

586

(1)

13.8 Interdigitation Design

586

(1)

13.9 Common Centroid and Interdigitation Design

587

(6)

13.9.1 Linewidth Control

588

(2)

13.9.2 Analog Design - Across Chip Line Width Variation (ACLU)

590

(1)

13.9.3 Passive Element Design

591

(1)

13.9.4 Resistor Element Design

591

(1)

13.9.5 Resistor Element Design: Dogbone Layout

591

(1)

13.9.6 Resistor Design - Analog Interdigitated Layout

592

(1)

13.10 Dummy Resistor Layout

593

(1)

13.11 Thermoelectric Cancelation Layout

593

(1)

13.12 Electrostatic Shield

593

(1)

13.13 Interdigitated Resistors and ESD Parasitics

594

(1)

13.14 Capacitor Element Design

595

(1)

13.15 Inductor Element Design

596

(1)

13.15.1 Quality Factor

597

(1)

13.16 ESD Failure in Inductors

597

(1)

13.17 Inductor Physical Variables

598

(1)

13.18 Inductor Element Design

599

(1)

13.19 Diode Design

599

(3)

13.19.1 Circular Diode Designs

600

(1)

13.19.2 Octagonal Diode Design

600

(1)

13.19.3 MOSFET Design

601

(1)

13.19.4 Multi-finger MOSFET with Dummy Fingers

601

(1)

13.20 Analog ESD Circuits

602

(5)

13.20.1 Analog ESD Devices and Circuits

602

(1)

13.20.2 Analog ESD Diodes

602

(1)

13.20.3 Analog Dual Diode and Series Diodes

602

(1)

13.20.4 Analog ESD: Dual Diode - Resistor

602

(3)

13.20.5 Dual Diode - Resistor - Dual Diode

605

(1)

13.20.6 Dual-diode Resistor - Grounded Gate MOSFET

606

(1)

13.20.6.1 Back-to-Back Diode Strings

606

(1)

13.21 ESD MOSFETs

607

(2)

13.21.1 Grounded Gate MOSFET

608

(1)

13.21.2 ESD Power Clamps - RC Triggered MOSFET

609

(1)

13.22 Receivers

609

(5)

13.22.1 Signal Bipolar Differential Receivers

610

(4)

13.23 CMOS Differential Receiver with Analog Layout Concepts

614

(6)

13.23.1 CMOS Differential Receiver Capacitance Loading

616

(1)

13.23.2 CMOS Differential Receiver ESD Mismatch

616

(1)

13.23.3 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout

617

(3)

13.24 Analog Differential Pair Common Centroid Design Layout - Signal-pin to Signal-pin and Parasitic ESD Elements

620

(4)

13.25 Summary and Closing Comments

624

(1)

References

624

(5)

14 ESD RF Design

629

(52)

14.1 Fundamental Concepts of ESD Design

629

(3)

14.2 Fundamental Concepts of RF ESD Design

632

(5)

14.3 RF CMOS Input Circuits

637

(10)

14.3.1 RF CMOS ESD Diode Networks

637

(4)

14.3.2 RF CMOS Diode String ESD Network

641

(2)

14.3.3 RF CMOS - Diode-inductor ESD Networks

643

(2)

14.3.4 RF Inductor-diode ESD Networks

645

(1)

14.3.5 RF Diode-inductor ESD Networks

646

(1)

14.4 RF CMOS Impedance Isolation LC Resonator ESD Networks

647

(1)

14.4.1 RF CMOS LC-diode ESD Networks

647

(1)

14.4.2 RF CMOS Diode-LC ESD Networks

648

(1)

14.5 RF CMOS LC-diode Networks Experimental Results

648

(2)

14.6 RF CMOS LNA ESD Design - Low Resistance ESD Inductor and ESD Diode Clamping Elements in H-configuration

650

(3)

14.7 RF CMOS T-coil Inductor ESD Input Network

653

(2)

14.8 RF CMOS Distributed ESD Networks

655

(1)

14.9 RF CMOS Distributed ESD-RF Networks

656

(1)

14.10 RF CMOS Distributed RF-ESD Networks Using Series Inductors and Dual-diode Shunts

656

(3)

14.11 RF CMOS Distributed RF-ESD Networks Using Series Inductors and MOSFET Parallel Shunts

659

(2)

14.12 RF CMOS Distributed ESD Networks - Transmission Lines and Co-planar Waveguides

661

(2)

14.13 RF CMOS - ESD and RF LDMOS Power Technology

663

(3)

14.14 Summary and Closing Comments

666

(1)

References

666

(15)

15 ESD Power Electronics Design

681

(28)

15.1 Reliability Technology Scaling and the Reliability Bathtub Curve

681

(5)

15.1.1 Reliability Design Box

681

(1)

15.1.2 Application Voltage and Voltage Metrics - Trigger Voltage, and Absolute Maximum Voltage

682

(1)

15.1.3 Safe Operating Area (SOA)

683

(1)

15.1.4 Electrical Safe Operating Area (E-SOA)

683

(1)

15.1.5 Thermal Safe Operating Area (T-SOA)

684

(1)

15.1.6 Transient Safe Operating Area

685

(1)

15.2 Input Circuitry

686

(16)

15.2.1 ESD Input Circuits

686

(1)

15.2.2 Analog Input Circuit Protection

686

(1)

15.2.3 High-voltage Analog Input Circuit Protection

686

(1)

15.2.4 Analog Input High-voltage Grounded Gate NMOS (GGNMOS)

686

(1)

15.2.5 Two-stage High-voltage Analog Input Circuit Protection

687

(1)

15.2.6 Analog ESD Output Circuits

687

(1)

15.2.7 Analog ESD Output Networks and Distinctions

688

(1)

15.2.8 Analog Open Drain ESD Output Networks

689

(1)

15.2.9 Analog ESD Ground-to-Ground Networks

689

(1)

15.2.10 Back-to-Back CMOS Diode String

690

(1)

15.2.11 HV GGNMOS Diode-configured Ground-to-Ground Network

690

(1)

15.2.12 ESD Silicon-controlled Rectifier Circuits

690

(1)

15.2.13 Unidirectional Silicon-controlled Rectifier (SCR)

690

(1)

15.2.14 Bi-directional Silicon-controlled Rectifier (SCR)

691

(1)

15.2.15 Medium-level Silicon-controlled Rectifier (MLSCR)

691

(1)

15.2.16 Low-voltage Triggered SCR (LVTSCR)

692

(1)

15.2.17 Analog and Power Technology with ESD Circuit Integration

693

(1)

15.2.18 Analog ESD - Isolated and Non-isolated Designs

693

(1)

15.2.19 Integrated Body Ties

693

(1)

15.2.20 Self-PROTECTING vs Non-self Protecting Designs

693

(1)

15.2.21 Lateral Diffused MOS (LDMOS) Circuits

693

(1)

15.2.22 LOCOS-defined LDMOS

694

(1)

15.2.23 RESURF Transistor

694

(1)

15.2.24 Advantages and Disadvantages of LOCOS-defined LDMOS Transistors

694

(1)

15.2.25 Shallow Trench Isolation (STI)-defined LDMOS

695

(1)

15.2.26 Shallow Trench Isolation (STI)-defined Isolated LDMOS

695

(1)

15.2.27 LDMOS Layout - Circular Design

696

(1)

15.2.28 LDMOS Transmission Line Pulse (TLP) I-V Characteristic

696

(1)

15.2.29 Drain-extended MOS (DeMOS) Circuits

697

(1)

15.2.30 DeNMOS

697

(1)

15.2.31 DeNMOS-SCR Transistor

698

(1)

15.2.32 Ultra-high Voltage LDMOS (UHV-LDMOS) Circuits

699

(1)

15.2.33 Ultra-high Voltage LDMOS (UHV-LDMOS)

699

(1)

15.2.34 UHV-LDMOS Layout - Circular Design

699

(1)

15.2.35 Ultra-high Voltage LDMOS (UHV-LDMOS) SCR

699

(3)

15.3 Summary and Closing Comments

702

(1)

References

702

(7)

16 ESD in Advanced CMOS

709

(74)

16.1 Interconnects and ESD

709

(1)

16.2 Aluminum Interconnects

710

(4)

16.3 Interconnects - Vias

714

(1)

16.3.1 Tapered Aluminum Via

714

(1)

16.4 Interconnects - Wiring

715

(4)

16.4.1 Titanium Interconnects Ti/Al/Ti

715

(4)

16.4.1.1 Copper Interconnects

715

(4)

16.5 Junctions

719

(6)

16.5.1 Abrupt Junctions

719

(1)

16.5.2 Low-doped Drains and ESD

720

(1)

16.5.3 Extension Implants

721

(1)

16.5.4 Gate Structures

722

(1)

16.5.4.1 Salicides and ESD

722

(1)

16.5.5 Salicide Resistance Model

723

(2)

16.6 Titanium Silicide

725

(6)

16.6.1 Molybdenum and Titanium Salicide

729

(1)

16.6.2 Cobalt Silicides

730

(1)

16.7 Shallow Trench Isolation

731

(3)

16.7.1 Isolation Structures and ESD

731

(1)

16.7.2 LOCOS Isolation

731

(3)

16.8 LOCOS-bound ESD Structures

734

(1)

16.9 LOCOS-bound p+/n-well Junction Diodes

734

(2)

16.10 LOCOS-bound n+ Junction Diodes

736

(39)

16.11 LOCOS-bound n-well/Substrate Diodes

737

(1)

16.12 LOCOS-bound Lateral N-Well to N-Well Bipolar ESD Element

738

(1)

16.13 LOCOS-bound Lateral N+ to N-well Bipolar ESD Element

738

(1)

16.14 LOCOS-bound Lateral pnp Bipolar ESD Element

739

(1)

16.15 LOCOS-bound Thick Oxide MOSFET ESD Element

739

(1)

16.16 Shallow Trench Isolation

739

(2)

16.16.1 Shallow Trench Isolation Pull-down

740

(1)

16.17 STI-bound ESD Structures

741

(5)

16.17.1 STI-bound p+/N-well Junctions

741

(3)

16.17.2 STI-bound N+ Junction Diodes

744

(1)

16.17.3 STI-bound N-well/Substrate Diodes

745

(1)

16.17.3.1 Substrates

745

(1)

16.17.4 Substrate P++ with Epitaxial Region

745

(1)

16.18 Substrate Modeling - Electrical and Thermal Discretization

746

(4)

16.19 Heavily Doped Substrates

750

(16)

16.19.1 Substrates: Heavily Doped Substrates

750

(1)

16.19.2 P-substrate Doping Scaling

751

(1)

16.19.2.1 Substrates: Low-doped Substrates

751

(1)

16.19.3 Diffused Wells

752

(1)

16.19.4 Diffused Well Vertical Profile

753

(2)

16.19.5 Retrograde and Vertically Modulated Wells

755

(1)

16.19.6 Retrograde and Vertically Modulated Wells

756

(4)

16.19.7 Retrograde Well Substrate Modulation

760

(6)

16.20 Retrograde Wells and ESD Scaling

766

(9)

16.20.1 Sub-collectors

769

(3)

16.20.2 Ballast Resistors

772

(3)

16.21 Triple Well and Isolated MOSFET CMOS

775

(4)

16.21.1 Deep Trench Isolation

776

(1)

16.21.2 Deep Trench as Guard Rings

777

(1)

16.21.3 Deep Trench and Latchup

778

(1)

16.21.4 Deep Trench and ESD Structures

778

(1)

16.22 Summary and Closing Comments

779

(1)

References

779

(4)

17 ESD in Silicon on Insulator

783

(38)

17.1 Silicon on Insulator (SOI) Technologies

783

(1)

17.1.1 SOI ESD Design Concepts

783

(1)

17.1.2 Distinction of SOI versus Bulk CMOS ESD Structures

783

(1)

17.1.3 Vertical Parasitic Devices

784

(1)

17.1.4 No Parasitic Devices

784

(1)

17.2 Elimination of CMOS Latchup

784

(1)

17.2.1 Isolation of CMOS NFETs and CMOS PFETs

785

(1)

17.3 Lack of Vertical Bipolar Transistors

785

(1)

17.4 Floating Gate Tie Downs

785

(1)

17.5 Physical Separation of MOSFETs from the Bulk Substrate

785

(1)

17.6 SOI ESD Design Fundamental Concepts

786

(5)

17.6.1 Spatial Uniformity

786

(1)

17.6.2 Avoidance of Localized Heating

787

(1)

17.6.3 Avoidance of SOI MOSFET Dielectric Breakdown

787

(1)

17.6.4 Avoidance of MOSFET Second Breakdown

787

(1)

17.6.5 SOI versus Bulk CMOS Layout Distinctions

787

(1)

17.6.6 SOI Design MOSFET with Body Contact: T-Shape Layout Style

788

(1)

17.6.7 Floating Body Issue

788

(1)

17.6.8 SOI MOSFET Body Contact

788

(1)

17.6.9 SOI T-shaped Lateral Diode

789

(1)

17.6.10 SOI ESD Double Diode Circuit with T- and H-shaped Devices

789

(1)

17.6.11 SOI ESD Double Diode Network with p-channel MOSFETS

790

(1)

17.6.12 SOI ESD Double Diode Network with Body Contacted n-channel MOSFET Devices

791

(1)

17.7 SOI Lateral Diode Structure

791

(1)

17.8 Transistors - Bulk versus SOI Technology

791

(5)

17.8.1 SOI Lateral Diode Design

792

(1)

17.8.2 SOI Lateral Diode Perimeter Design

793

(1)

17.8.3 SOI Lateral Diode Channel Length Design

793

(1)

17.8.4 SOI Lateral p+/n-/n+ Diode Structure

793

(1)

17.8.5 SOI Lateral p+/p-/n+ Diode Structure

794

(1)

17.8.6 SOI Lateral p+/p-/n-/n+ Diode Structure

794

(1)

17.8.7 SOI Lateral Ungated p+/p-/n-/n+ Diode Structure

795

(1)

17.8.8 SOI Lateral Diode Structures and SOI MOSFET Halos

795

(1)

17.9 SOI Buried Resistors (BR) Elements

796

(1)

17.10 Dynamic Threshold MOS (DTMOS) SOI MOSFET

797

(1)

17.11 SOI P+ Body Contact Abutting n+ Drain

798

(1)

17.11.1 P+ Body Contact Separated from n+ Drain

798

(1)

17.11.2 Polysilicon Body Isolation from n+ Contact

798

(1)

17.12 Transmission Line Pulse (TLP) Testing of SOI Diode Designs

798

(1)

17.13 SOI ESD with MOSFET Drain and Body Width Ratio Variation

799

(1)

17.14 SOI Dual-Gate MOSFET Structure

799

(1)

17.15 SOI ESD Design - Mixed Voltage T-Shape Layout Style

800

(2)

17.15.1 SOI ESD Design: Mixed Voltage Diode Strings

801

(1)

17.15.2 Advantages and Disadvantages of Mixed Voltage SOI Diode Strings

801

(1)

17.16 SOI ESD Design: Double Diode Network

802

(1)

17.17 Bulk to SOI ESD Design Remapping

803

(1)

17.18 SOI ESD Diode Design Parameters

804

(4)

17.18.1 SO! ESD Diode Device versus Diode Perimeter

804

(1)

17.18.2 SOI ESD as a Function of Polysilicon Length

804

(2)

17.18.2.1 SOI Multi-finger ESD Diode Structure

804

(1)

17.18.2.2 SOI ESD Structure Cross-section

805

(1)

17.18.3 Layout of SOI ESD Double Diode Structure

806

(27)

17.18.3.1 SOI ESD Results as a Function of ESD Structure Perimeter

806

(1)

17.18.3.2 SOI ESD Results as a Function of Finger Number

807

(1)

17.19 SOI ESD Design in Mixed Voltage Interface Environments

808

(1)

17.20 Comparison of Bulk with SOI ESD Results

809

(1)

17.21 SOI ESD Design with Aluminum Interconnects

810

(2)

17.22 SOI ESD Design with Copper Interconnects

812

(1)

17.23 SOI ESD Design with Gate Circuitry

813

(2)

17.24 Summary and Closing Comments

815

(1)

References

815

(6)

18 ESD in Analog Circuits

821

(44)

18.1 Analog Design Circuits

821

(1)

18.2 Single-ended Receivers

822

(1)

18.3 Schmitt Trigger Receivers

822

(1)

18.4 Differential Receivers

822

(2)

18.5 Comparators

824

(1)

18.6 Current Sources

825

(1)

18.7 Current Mirrors

825

(1)

18.8 Widlar Current Mirror

826

(1)

18.9 Wilson Current Mirror

826

(1)

18.10 Voltage Regulators

827

(1)

18.11 Buck Converters

828

(1)

18.12 Boost Converters

828

(1)

18.13 Buck-Boost Converters

829

(1)

18.14 Cuk Converters

830

(1)

18.15 Voltage Reference Circuits

830

(1)

18.16 Brokaw Bandgap Voltage Reference

830

(1)

18.17 Converters

831

(1)

18.18 Analog-to-Digital Converter (ADC)

831

(1)

18.19 Digital-to-Analog Converters (DAC)

832

(1)

18.20 Oscillators

832

(1)

18.21 Phase Lock Loop (PLL) Circuits

832

(1)

18.22 Delay Locked Loop (DLL)

833

(1)

18.23 Analog and ESD Design Synthesis

833

(3)

18.23.1 Early ESD Failures in Analog Design

833

(1)

18.23.2 Mixed Voltage Interface - Voltage Regulator Failures

833

(1)

18.23.3 N-channel MOSFET Voltage Regulator

834

(1)

18.23.4 P-channel MOSFET Voltage Regulator

835

(20)

18.23.4.1 ESD Protection Solution for Voltage Regulator - GGNMOS ESD Bypass Between Power Rails

835

(1)

18.23.4.2 ESD Protection Solution for Voltage Regulator - Series Diode String ESD Bypass

836

(1)

18.24 Analog Chip Architecture - Separation of Analog Power from Digital Power, AVDD-DVDD

836

(1)

18.25 ESD Failure in Phase Lock Loop (PLL) and System Clock

837

(1)

18.26 ESD Failure in Current Mirrors

837

(1)

18.27 ESD Failure in Schmitt Trigger Receivers

838

(2)

18.28 ESD Design Practice - Prevent ESD Failure in Schmitt Trigger

840

(1)

18.29 Analog-Digital Architecture: Isolated Digital and Analog Domains

841

(1)

18.30 ESD Protection Solution - Connectivity of AVDD-to-VDD

842

(1)

18.31 ESD Solution: Connectivity of AVss-to-DVss

843

(1)

18.32 Digital and Analog Domain with ESD Power Clamps

843

(3)

18.33 Digital and Analog Domain with Master-Slave ESD Power Clamps

846

(1)

18.34 High Voltage, Digital, and Analog Domain Floorplan

846

(1)

18.35 Floor-planning of Digital and Analog

846

(3)

18.36 Inter-domain Signal Lines ESD Failures

849

(1)

18.37 Digital-to-Analog Signal Line ESD Failures

849

(2)

18.38 Digital-to-Analog Core Spatial Isolation

851

(1)

18.39 Digital-to-Analog Core Ground Coupling

851

(1)

18.40 Digital-to-Analog Core Resistive Ground Coupling

852

(1)

18.41 Digital-to-Analog Core Diode Ground Coupling

852

(1)

18.42 Domain-to-Domain Signal Line ESD Networks

852

(1)

18.43 Domain-to-Domain Third-party Coupling Networks

853

(1)

18.44 Domain-to-Domain Cross-domain ESD Power Clamp

854

(1)

18.45 Digital-to-Analog Domain Moat

855

(1)

18.46 Analog and ESD Circuit Integration

855

(1)

18.46.1 Analog and Power Technology and ESD Circuit Integration

855

(1)

18.46.2 Analog ESD - Isolated and Non-isolated Designs

855

(1)

18.47 Integrated Body Ties

856

(1)

18.48 Self-Protecting vs Non-self Protecting Designs

856

(1)

References

856

(9)

19 ESD in RF CMOS

865

(26)

19.1 CMOS and ESD

865

(1)

19.2 RF CMOS

865

(1)

19.3 RF CMOS and ESD

865

(1)

19.4 RF CMOS ESD Failure Mechanisms

865

(1)

19.5 RF CMOS - ESD Device Comparisons

866

(1)

19.6 RF ESD Metrics

867

(1)

19.7 Grounded Gate n-channel MOSFET versus STI Diode

868

(1)

19.8 Silicon-controlled Rectifier

869

(1)

19.9 SCR versus GGNMOS

869

(1)

19.10 Shallow Trench Isolation and Polysilicon Gated Diodes

869

(1)

19.11 RF ESD Design

870

(1)

19.12 RF ESD Design Layout - Circular RF ESD Devices

870

(1)

19.13 Disadvantage of RF ESD Circular Element

871

(1)

19.14 RF ESD Design - ESD Wiring Design

872

(1)

19.15 RF ESD Design - Loading Capacitance

872

(1)

19.16 Metal Capacitance

873

(1)

19.17 Analog Metal (AM)

873

(1)

19.18 RF ESD Design Practices

874

(1)

19.19 RF Passives - ESD and Schottky Barrier Diodes

874

(1)

19.19.1 Silicon Schottky Barrier Diodes

874

(1)

19.20 Schottky Barrier Diodes and Metallurgy

875

(1)

19.21 Silicon Germanium Schottky Barrier Diodes

876

(1)

19.22 Schottky Barrier RF ESD Design Practice

877

(1)

19.23 RF Passives - ESD and Inductors

877

(1)

19.24 Quality Factor, Q

878

(1)

19.25 Incremental Model of an Inductor

878

(1)

19.26 Inductor Coil Parameters

878

(4)

19.26.1 ESD Testing of RF Inductors

880

(1)

19.26.2 Inductor Coil Geometry and ESD

880

(1)

19.26.3 Steps and Process of Inductor Failure

881

(1)

19.27 RF Passives - ESD and Capacitors

882

(1)

19.28 Capacitors and RF Applications

882

(1)

19.29 Capacitors in ESD Networks

882

(1)

19.30 Types of Radio Frequency Capacitors

883

(1)

19.31 Metal-Oxide-Semiconductor and Metal-Insulator-Metal Capacitors

883

(1)

19.32 Varactors and Hyper-abrupt Junction Varactor Capacitors

884

(1)

19.33 Metal-ILD-Metal Capacitors

884

(1)

19.34 Vertical Parallel Plate (VPP) Capacitors

884

(1)

19.35 Tips: ESD RF Design Practices for Capacitors

885

(1)

19.36 Summary and Closing Comments

886

(1)

Problems

886

(2)

References

888

(3)

20 ESD in Silicon Germanium

891

(44)

20.1 Heterojunctions Bipolar Transistors

891

(1)

20.2 Silicon Germanium

891

(1)

20.3 Silicon Germanium HBT Devices

892

(1)

20.4 Silicon Germanium Device Structure

893

(1)

20.5 Silicon Germanium Film Deposition

894

(1)

20.6 Silicon Germanium Emitter-Base Region

895

(1)

20.7 Silicon Germanium Physics

895

(1)

20.8 Silicon Germanium Bandgap

896

(1)

20.9 Silicon Germanium Intrinsic Temperature

896

(1)

20.10 Position-dependent Silicon Germanium Profile

896

(1)

20.11 Position-dependent Intrinsic Temperature

897

(1)

20.12 SiGe Collector Current with Graded Germanium Concentration

897

(1)

20.13 Silicon Germanium ESD and Time Constants

898

(1)

20.14 Silicon Germanium Base Transit Time

898

(1)

20.15 Silicon Germanium Breakdown Voltages

898

(1)

20.16 Silicon Germanium ESD Measurements

899

(1)

20.17 Silicon Germanium Collector-to-Emitter ESD Stress

899

(1)

20.18 Transmission Line Pulse Testing of Silicon Germanium HBT

899

(1)

20.19 Transmission Line Pulse (TLP) I-V Characteristic

899

(2)

20.20 Wunsch-Bell Characteristic of Silicon Germanium HBT

901

(1)

20.21 Comparison of Silicon Germanium HBT and Silicon BJT

901

(1)

20.22 Wunsch-Bell Characteristic of SiGe HBT versus Si BJT

902

(2)

20.23 Intrinsic Base Resistance in SiGe HBT

904

(1)

20.24 SiGe HBT Electro-thermal HBM Simulation of Collector-Emitter Stress

904

(1)

20.25 Silicon Germanium Transistor Emitter-Base Design

905

(2)

20.26 Epitaxial-Base Hetero-Junction Bipolar Transistor (HBT) Emitter-Base Design

907

(1)

20.27 Self-aligned Silicon Germanium HBT Device

907

(1)

20.28 Non-Self Aligned Silicon Germanium HBT

908

(1)

20.29 Emitter-Base Design RF Frequency Performance Metrics

908

(1)

20.30 SiGe HBT Emitter-Base Resistance Model

909

(1)

20.31 SiGe HBT Emitter-Base Design and Silicide Placement

909

(1)

20.32 Silicide Material and ESD

910

(1)

20.33 Titanium Silicide and ESD

911

(2)

20.34 Cobalt Salicide

913

(1)

20.35 Self-aligned (SA) Emitter Base Design

914

(3)

20.36 Non-Self Aligned (NSA) Emitter Base Design

917

(1)

20.37 Non-Self Aligned HBT Human Body Model (HBM) Step Stress

918

(1)

20.38 Transmission Line Pulse (TLP) Step Stress

918

(3)

20.39 RF Testing of SiGe HBT Emitter-Base Configuration

921

(2)

20.40 Unity Current Gain Cutoff Frequency - Collector Current Plots

923

(1)

20.41 fmAx and fT

924

(1)

20.42 Electrothermal Simulation of Emitter-Base Stress

925

(1)

20.43 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data

926

(1)

20.44 Silicon Germanium HBT Multiple-emitter Study

927

(1)

20.45 RF ESD Design Practice

927

(1)

20.46 Silicon Germanium ESD Failure Mechanisms

928

(1)

20.47 Summary and Closing Comments

928

(1)

References

928

(7)

21 ESD in Silicon Germanium Carbon

935

(16)

21.1 Heterojunctions and Silicon Germanium Carbon Technology

935

(1)

21.2 Silicon Germanium Carbon

935

(2)

21.3 Silicon Germanium Carbon Collector-Emitter ESD Measurements

937

(3)

21.4 Silicon Germanium Transistor Emitter-Base Design

940

(3)

21.5 Silicon Germanium Carbon - ESD-Induced S-Parameter Degradation

943

(2)

21.6 Silicon Germanium Carbon ESD Failure Mechanisms

945

(1)

21.7 Summary and Closing Comments

945

(1)

References

946

(5)

22 ESD in GaAs

951

(20)

22.1 Gallium Arsenide Technology and ESD

951

(1)

22.2 Gallium Arsenide Energy-to-Failure, and Power-to-Failure

951

(3)

22.3 Gallium Arsenide ESD Failures in Active and Passive Elements

954

(1)

22.3.1 Interconnects

954

(1)

22.3.2 Thin Film Metal Resistors

955

(1)

22.3.3 Metal-Insulator-Metal (MIM) Capacitors

955

(1)

22.4 Gallium Arsenide HBT Devices and ESD

955

(1)

22.5 Gallium Arsenide HBT Device ESD Results

956

(1)

22.6 Gallium Arsenide HBT Diode Strings

957

(2)

22.7 Gallium Arsenide HBT-based Passive Elements

959

(1)

22.8 GaAs HBT Base-Collector Varactor

959

(1)

22.9 Gallium Arsenide Technology Table of Failure Mechanisms

960

(1)

22.10 Application - GaAs Power Amplifier in a Cell Phone

961

(4)

22.10.1 Problems

961

(1)

22.10.2 Indium Gallium Arsenide and ESD

961

(3)

22.10.3 Indium Phosphide (InP) and ESD

964

(1)

22.10.4 ESD GaN Failure Mechanisms

965

(1)

22.11 Summary and Closing Comments

965

(1)

Questions

965

(1)

References

966

(5)

23 ESD in Bulk and SOI FINFET

971

(8)

23.1 Early FinFET Structures

971

(1)

23.2 FinFET Structure and Design Parameters

971

(2)

23.3 FinFET Parameters

973

(4)

23.3.1 FinFET Channel Length

973

(1)

23.3.2 Effective Film Thickness

973

(1)

23.3.3 Temperature

974

(1)

23.3.4 Self-heating in FinFET Issues

974

(1)

23.3.5 FinFET Current Distribution

974

(1)

23.3.6 FinFET Current Constriction

974

(3)

23.4 Summary and Closing Comments

977

(1)

References

977

(2)

24 MEMs

979

(12)

24.1 Micro-electromechanical (MEM) Devices

979

(1)

24.2 ESD Concerns in Micro-electromechanical (MEM) Devices

980

(2)

24.2.1 ESD Failure in MEM Devices - Electrical Breakdown

980

(1)

24.2.2 MEM Structures - Gap Variation

980

(1)

24.2.3 Stiction

980

(1)

24.2.4 Residual Charge

981

(1)

24.2.5 Mechanical Deformation

981

(1)

24.2.5.1 Micro-motors

981

(1)

24.2.6 ESD Concerns in Micro-motors

981

(1)

24.2.7 Nano-welding

981

(1)

24.2.8 Residual Particles

981

(1)

24.3 Actuators

982

(2)

24.3.1 Torsional Ratcheted Actuator

982

(1)

24.3.2 Comb-to-Comb ESD Failure

983

(1)

24.3.3 Charged Device Model

983

(1)

24.4 Micro-electromechanical (MEM) RF Switches

984

(1)

24.4.1 Radio Frequency (RF) Switches

984

(1)

24.4.2 RF Switch ESD Concerns

984

(1)

24.4.3 Mechanical Deformation

984

(1)

24.4.4 Mechanical Failure

984

(1)

24.4.5 Osterberg Model

984

(1)

24.4.6 Collapse Voltage

985

(1)

24.5 Micro-electromechanical (MEM) Mirrors

985

(4)

24.5.1 Micro-mirrors

985

(2)

24.5.2 ESD Concerns in Micro-electromechanical (MEM) Mirrors

987

(2)

24.5.3 Mechanical Motion

989

(1)

24.5.4 Mirror-to-Mirror Failures

989

(1)

24.6 Summary and Closing Comments

989

(1)

References

989

(2)

25 Magnetic Recording

991

(12)

25.1 Magnetic Recording Technology

991

(4)

25.1.1 Magnetic Recording Industry

991

(1)

25.1.2 Magneto-Resistor (MR) Structure

991

(2)

25.1.2.1 Magneto-Resistor Head ESD Damage - Stripe Resistance Shift

991

(2)

25.1.3 MR Stripe to Magnetic Shield ESD Failures

993

(1)

25.1.4 Magneto-Recording Head - Write Coil ESD Failure

993

(1)

25.1.5 Giant Magneto-Resistors (GMR)

993

(1)

25.1.5.1 ESD Failure Mechanisms in GMR Heads

994

(1)

25.1.6 Tunneling Magnetic Resistor (TMR)

994

(1)

25.2 Summary and Closing Comments

995

(1)

References

995

(8)

26 Photomasks

1003

(10)

26.1 Photomasks and Reticles

1003

(1)

26.1.1 Photomasks

1003

(1)

26.2 ESD Concerns in Photomasks

1003

(1)

26.2.1 Electrostatic Charging on Photomasks

1003

(1)

26.2.2 ESD Discharge on a Photomask

1004

(1)

26.3 Avalanche Breakdown in Photomasks

1004

(3)

26.3.1 Avalanche Phenomena - Townsend Breakdown Model

1004

(2)

26.3.2 Avalanche Breakdown - Paschen Breakdown Model

1006

(1)

26.4 Electrical Model in Photomasks

1007

(1)

26.4.1 RLC Response - Montoya, Levit, and Englisch Model

1007

(1)

26.5 Failure Defects in Photomasks

1008

(3)

26.5.1 Mask Defects

1008

(1)

26.5.2 Mask Inspection Tools

1008

(3)

26.6 Summary and Closing Comments

1011

(1)

References

1011

(2)

Appendix Table of Acronyms

1013

A Glossary of Terms - EMC Terminology

1015

(2)

B Appendix B. ESD Standards

1017

(4)

B.1 ESD Association

1017

(1)

B.2 International Organization of Standards

1018

(1)

B.2.1 IEC

1018

(1)

B.2.2 RTCA

1018

(1)

B.3 Department of Defense

1018

(1)

B.4 Military Standards

1019

(1)

B.5 Airborne Standards and Lightning

1019

(2)

C Index

1021

(34)

D Wiley Series in Electrostatic Discharge (ESD) and Electrical Overstress (EOS)

1055

(2)

D.1 Additional Wiley Texts

1055

(2)

E ESD Design Rules

1057

(4)

E.1 ESD Design Rule Check (DRC)

1057

(1)

E.2 Electrostatic Discharge (ESD) Layout Versus Schematic (LVS) Verification

1058

(1)

E.3 ESD Electrical Rule Check (ERC)

1059

(2)

F Guard Ring Design Rules

1061

(6)

F.1 Latchup Design Rule Checking (DRC) and Guard Rings

1061

(2)

F.1.1 External Latchup

1063

(1)

F.2 Latchup Electrical Rule Check (ERC)

1063

(1)

F.2.1 N-well Contact to p-channel MOSFET Resistance

1063

(1)

F.2.2 P-well or p-substrate Contact to n-channel MOSFET Resistance

1064

(1)

F.3 Guard Ring Resistance

1064

(3)

G EOS Design Rules and Checklist

1067

(2)

G.1 Electrical Overstress (EOS) Design Rule Checking

1067

(1)

G.2 Electrical Overstress (EOS) Layout Versus Schematic (LVS) Verification

1067

(1)

G.3 Electrical Overstress (EOS) Electrical Rule Check (ERC)

1068

(1)

H Latchup Design Rules

1069

(8)

H.1 Latchup Design Rule Checking (DRC)

1069

(3)

H.2 Latchup Electrical Rule Check (ERC)

1072

(5)

H.2.1 N-well Contact to p-channel MOSFET Resistance

1072

(1)

H.2.2 P-Well or P-Substrate Contact to N-Channel MOSFET Resistance

1072

(1)

H.2.3 Guard Ring Resistance

1072

(5)

I ESD Cookbook

1077

(2)

I.1 Electrostatic Discharge (ESD) Cookbook

1077

(2)

I.1.1 Table of Pin Types

1077

(2)

J EOS Cookbook

1079

(2)

J.1 Electrical Overstress (EOS) Cookbook

1079

(2)

J.1.1 Table of Pin Types

1080

(1)

K Latchup Cookbook

1081

(6)

K.1 Latchup Design Rule Checking (DRC)

1081

(2)

K.2 Latchup Electrical Rule Check (ERC)

1083

(4)

K.2.1 N-well Contact to p-channel MOSFET Resistance

1083

(1)

K.2.2 P-well or p-substrate Contact to n-channel MOSFET Resistance

1084

(1)

K.2.3 Guard Ring Resistance

1084

(3)

L ESD Design and Release Check List

1087

(2)

L.1 ESD Design Release

1087

(1)

L.2 Electrostatic Discharge (ESD) Checklists

1087

(2)

M EOS Design and Release Checklist

1089

(4)

M.1 Electrical Overstress (EOS) and ESD Design Release

1089

(1)

M.2 Electrical Overstress (EOS) Design Release Process

1089

(1)

M.3 Electrical Overstress (EOS) Checklists

1090

(1)

M.4 An EOS Checklist

1091

(2)

N Latchup Design and Release Checklist

1093

N.1 Latchup Design Rule Checking (DRC)

1093

(2)

N.2 Latchup Electrical Rule Checking (ERC)

1095

(1)

N.2.1 N-well Contact to p-channel MOSFET Resistance

1095

(1)

N.2.2 P-well or P-Substrate Contact to n-channel MOSFET Resistance

1095

(1)

N.3 Latchup Checklists

1095

(1)

N.4 A Latchup Design and Release Checklist

1096

Index

109

Steven H. Voldman is the first IEEE Fellow for contributions in ESD protection in CMOS, SOI, and Silicon Germanium technology. He has been at the forefront of every major development in semiconductor technology over the past thirty years.

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