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1 | (14) |
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2 | (2) |
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1.1.1 Conventional AC Grids |
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2 | (1) |
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1.1.2 DC Transmission Lines |
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2 | (1) |
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3 | (1) |
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4 | (1) |
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1.2 Topologies and Functionality |
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4 | (3) |
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1.2.1 Medium- and High-Voltage Converters |
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4 | (2) |
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1.2.2 The Voltage Control in Grid-Side Converters |
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6 | (1) |
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1.2.3 Current Control in Grid-Side Converters |
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6 | (1) |
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1.3 The Impact of Grid-Side Converters |
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7 | (3) |
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1.3.1 DC Bias and Line Harmonics |
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7 | (1) |
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1.3.2 Behavioral Model of Load-Side Converters |
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8 | (1) |
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1.3.3 Behavioral Model of Source-Side Converters |
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9 | (1) |
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1.4 Control Techniques for Grid-Side Converters |
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10 | (5) |
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1.4.1 Robust and Error-Free Feedback Acquisition |
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10 | (1) |
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1.4.2 High Bandwidth Digital Current Controllers |
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11 | (1) |
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1.4.3 Suppression of Low-Order Harmonics |
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12 | (1) |
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1.4.4 Synchronization and Power-Frequency Change |
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12 | (1) |
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13 | (2) |
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15 | (46) |
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2.1 Two-Level Inverters with Symmetrical PWM |
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16 | (12) |
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2.1.1 Pulse Width Modulation |
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16 | (2) |
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2.1.2 Pulsed Voltages and the Current Ripple |
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18 | (1) |
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2.1.3 Star Connection and Line Voltages |
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19 | (3) |
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2.1.4 Symmetrical and Asymmetrical PWM Carrier |
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22 | (1) |
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23 | (1) |
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2.1.6 The Output Voltage Waveform and Spectrum |
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24 | (4) |
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2.2 Space Vector Modulation with DI and DD Sequences |
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28 | (14) |
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2.2.1 The Switching States and the Voltage Vectors |
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28 | (3) |
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2.2.2 The Switching Sequence and Dwell Times |
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31 | (3) |
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2.2.3 DD Switching Sequence |
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34 | (1) |
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2.2.4 DI Switching Sequence |
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34 | (2) |
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2.2.5 The Maximum Output Voltage with DI Sequence |
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36 | (3) |
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2.2.6 Symmetrical PWM with Common Mode Signals |
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39 | (3) |
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2.3 Lockout Time Error and Compensation |
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42 | (5) |
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2.3.1 Implementation of the Lockout Time |
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42 | (2) |
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2.3.2 The Voltage Error Caused by the Lockout Time |
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44 | (1) |
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2.3.3 Compensation of the Lockout Time Voltage Errors |
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45 | (2) |
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2.4 Design of the Output L Filters and LCL Filters |
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47 | (6) |
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2.4.1 The rms Value of the Current Ripple |
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47 | (1) |
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2.4.2 The L-Type Output Filter |
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48 | (1) |
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2.4.3 The LCL-Type Output Filter |
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49 | (4) |
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2.5 Multilevel Inverters and Their PWM Techniques |
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53 | (7) |
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2.5.1 Three-Level Inverters |
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54 | (1) |
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2.5.2 The Phase Voltages and Line Voltages |
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55 | (2) |
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2.5.3 Space Vector Modulation in Multilevel Inverters |
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57 | (3) |
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60 | (1) |
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3 Acquisition of the Feedback Signals |
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61 | (42) |
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3.1 Current Sensors and Galvanic Insulation |
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61 | (10) |
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3.1.1 Shunt-Based Current Sensing |
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62 | (1) |
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3.1.2 Current Transformers |
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63 | (3) |
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66 | (3) |
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3.1.4 Hall Effect and Fluxgate Current Sensors |
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69 | (2) |
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3.2 Analogue Filtering and Sampling |
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71 | (22) |
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3.2.1 Gain and Offset Adjustment |
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71 | (4) |
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3.2.2 Analogue-to-Digital Conversion |
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75 | (1) |
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76 | (4) |
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3.2.4 The Alias-Free Sampling |
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80 | (7) |
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3.2.5 Low-Pass RC Filter as an Anti-alias Filter |
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87 | (2) |
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3.2.6 Second-Order Low-Pass Anti-alias Filter |
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89 | (1) |
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3.2.7 Center-Pulse Sampling |
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90 | (3) |
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3.3 Oversampling-Based Feedback Acquisition |
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93 | (10) |
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3.3.1 One-PWM-Period Averaging |
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93 | (1) |
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3.3.2 Oversampling and Averaging |
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94 | (1) |
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3.3.3 Practical Implementation |
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95 | (1) |
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3.3.4 Pulse Transfer Function of the Feedback Subsystem |
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96 | (2) |
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3.3.5 Current Measurement in LCL Filters |
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98 | (5) |
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4 Introduction to Current Control |
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103 | (26) |
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4.1 The Model of the Load |
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105 | (5) |
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4.1.1 The Three-Phase Load |
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105 | (1) |
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4.1.2 The Model of the Load in α-β Coordinate Frame |
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106 | (2) |
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4.1.3 The Model of the Load in d-q Frame |
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108 | (2) |
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4.2 The PI Current Controllers |
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110 | (4) |
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4.2.1 The PI Controller in α-β Frame |
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111 | (1) |
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4.2.2 The PI Controller in d-q Frame |
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112 | (2) |
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4.3 Decoupling Current Controller in d-q Frame |
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114 | (2) |
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4.3.1 Basic Principles of Internal Model Control |
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115 | (1) |
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4.3.2 Decoupling Controller |
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115 | (1) |
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4.4 Resonant Current Controllers |
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116 | (5) |
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4.4.1 Transformation of the d-q Frame Controller in α-β Frame |
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117 | (1) |
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4.4.2 The Resonant Controller in α-β Frame |
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118 | (1) |
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4.4.3 Dynamic Properties of the Resonant Controller |
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119 | (2) |
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4.5 Disturbance Rejection |
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121 | (8) |
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4.5.1 Disturbance Rejection with d-q Frame PI Controller |
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121 | (2) |
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4.5.2 Active Resistance Feedback |
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123 | (6) |
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5 Discrete-Time Synchronous Frame Controller |
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129 | (28) |
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5.1 Discrete-Time Controller with Center-Pulse Sampling |
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130 | (9) |
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5.1.1 The Pulse Transfer Function of the Load |
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130 | (2) |
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5.1.2 Design of the Controller Structure |
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132 | (2) |
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134 | (2) |
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5.1.4 Disturbance Rejection |
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136 | (3) |
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5.2 Current Controller with Oversampling-Based Feedback |
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139 | (5) |
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5.2.1 The Pulse Transfer Function of the Feedback Path |
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139 | (1) |
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5.2.2 Design of the Controller Structure |
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140 | (1) |
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141 | (2) |
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5.2.4 Disturbance Rejection |
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143 | (1) |
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5.3 Current Controllers with Series Compensator |
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144 | (4) |
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5.3.1 Synchronous Sampling with Series Compensator |
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144 | (2) |
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5.3.2 One-PWM-Period Averaging with Series Compensator |
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146 | (2) |
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5.4 Experimental Runs with IMC-Based Controllers |
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148 | (9) |
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5.4.1 Parameters of the Experimental Setup |
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149 | (1) |
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5.4.2 Experimental Results |
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149 | (8) |
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6 Scheduling of the Control Tasks |
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157 | (26) |
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157 | (4) |
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6.1.1 Conventional Scheduling |
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158 | (2) |
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6.1.2 Advanced Scheduling |
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160 | (1) |
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6.2 Pulse Transfer Function with Advanced Scheduling |
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161 | (6) |
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6.2.1 Pulse Transfer Function of the Load |
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161 | (2) |
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6.2.2 Design of the Controller Structure |
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163 | (1) |
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6.2.3 Closed-Loop and Disturbance Transfer Functions |
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163 | (2) |
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6.2.4 Parameter Setting and the Closed-Loop Performance |
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165 | (2) |
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6.3 Advanced Scheduling with Series Compensator |
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167 | (3) |
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6.3.1 Closed-Loop and Disturbance Transfer Functions |
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167 | (2) |
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6.3.2 Parameter Setting and the Closed-Loop Performance |
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169 | (1) |
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170 | (13) |
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6.4.1 The Impact of the Computation Delay |
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171 | (1) |
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6.4.2 Input Step Response |
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172 | (1) |
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6.4.3 Robustness Against the Parameter Changes |
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173 | (10) |
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183 | (28) |
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7.1 Active Resistance Feedback |
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183 | (5) |
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7.1.1 Equivalent Load with Synchronous Sampling |
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184 | (1) |
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7.1.2 Equivalent Load with One-PWM-Period Averaging |
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185 | (1) |
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7.1.3 Equivalent Load with the Advanced Scheduling |
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186 | (1) |
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7.1.4 The Range of Stable Ra Gains |
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187 | (1) |
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7.2 Design of Decoupling Controllers |
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188 | (4) |
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7.2.1 Conventional Scheduling with Synchronous Sampling |
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188 | (2) |
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7.2.2 Conventional Scheduling with Feedback Averaging |
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190 | (1) |
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7.2.3 Advanced Scheduling with Feedback Averaging |
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191 | (1) |
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7.3 Disturbance Suppression in Synchronous Frame |
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192 | (4) |
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7.3.1 The Applicable Range of Ra Gains |
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193 | (1) |
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7.3.2 Simulation of the Dynamic Response |
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194 | (1) |
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194 | (2) |
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7.4 Disturbance Suppression in Stationary Frame |
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196 | (6) |
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7.4.1 The Frequency Characteristic of Ys with Ra = 0 |
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199 | (1) |
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7.4.2 The Frequency Characteristic of Ys with Ra > 0 |
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199 | (3) |
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202 | (4) |
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7.5.1 Parameters of the Experimental Setup |
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203 | (1) |
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7.5.2 Input Step Response |
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203 | (1) |
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7.5.3 Disturbance Rejection |
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204 | (2) |
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206 | (5) |
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8 Synchronization and Control |
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211 | (46) |
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212 | (6) |
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8.1.1 The Phase Detector with a Multiplier |
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213 | (1) |
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8.1.2 Phase Detector with XOR Function |
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214 | (1) |
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8.1.3 The Phase Detector Based on the d-Axis Voltage |
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214 | (2) |
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8.1.4 The Closed-Loop Operation of the PLL |
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216 | (2) |
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8.2 Dynamic Response of Grid-Side Converters |
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218 | (14) |
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8.2.1 Dynamic Response of Conventional Generators |
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218 | (5) |
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8.2.2 The Impact of the Damper Winding |
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223 | (1) |
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8.2.3 Dynamic Response of the PLL-Driven Converter |
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224 | (4) |
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8.2.4 Emulation of Synchronous Machines |
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228 | (2) |
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230 | (2) |
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8.3 DC-Bus Control and Droop Control |
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232 | (5) |
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233 | (1) |
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234 | (3) |
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8.4 DC-Bias Detection and Suppression |
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237 | (20) |
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8.4.1 Sensitivity of Distribution Transformers to DC-Bias |
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238 | (3) |
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8.4.2 Peak-Detection Methods |
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241 | (3) |
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8.4.3 Optimum Form of the Core |
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244 | (4) |
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8.4.4 Detection Based on Even Harmonics |
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248 | (2) |
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8.4.5 Closed-Loop DC-Bias Suppression |
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250 | (7) |
References |
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257 | (2) |
Bibliography |
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259 | (2) |
Index |
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261 | |