Preface |
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xix | |
Acknowledgment |
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xxiii | |
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1 An Overview of Mixed-Signal, Embedded System Design |
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1 | (50) |
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1.1 Embedded Applications |
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2 | (10) |
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1.2 Embedded Architectures |
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12 | (7) |
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19 | (4) |
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1.4 Embedded Systems Market |
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23 | (1) |
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1.5 Embedded Design Example: Fan Control System |
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23 | (19) |
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1.5.1 Description of the Fan Controller System |
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24 | (5) |
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1.5.2 Design of the Fan Controller System |
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29 | (13) |
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42 | (1) |
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43 | (2) |
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1.8 Recommended Exercises |
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45 | (6) |
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2 Microcontroller Architecture |
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51 | (52) |
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2.1 Microcontroller Architecture |
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51 | (40) |
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2.1.1 Microcontroller Addressing Modes |
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53 | (3) |
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56 | (35) |
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91 | (5) |
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96 | (2) |
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2.4 Recommended Exercises |
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98 | (5) |
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3 Hardware and Software Subsystems of Mixed-Signal Architectures |
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103 | (48) |
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3.1 Subsystems of the PSoC Mixed-Signal Architecture |
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104 | (10) |
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3.1.1 PSoC Hardware Components |
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106 | (4) |
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3.1.2 PSoC Software Components |
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110 | (4) |
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3.2 The PSoC Interrupt Subsystem |
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114 | (10) |
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3.2.1 Case Study: Tachometer Interrupt Service Routines |
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117 | (7) |
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124 | (4) |
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128 | (15) |
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143 | (3) |
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146 | (3) |
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3.7 Recommended Exercises |
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149 | (2) |
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4 Performance Improvement by Customization |
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151 | (56) |
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4.1 Introduction to Application-Specific Customization |
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152 | (3) |
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4.2 Design Methodology for Architecture Customization |
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155 | (18) |
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4.2.1 System Specification and Profiling |
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155 | (5) |
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4.2.2 System Partitioning and Implementation |
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160 | (13) |
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4.3 Programmable Digital Blocks |
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173 | (11) |
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176 | (6) |
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182 | (1) |
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183 | (1) |
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4.4 Customized PSoC Digital Blocks |
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184 | (17) |
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4.4.1 Pulse Width Modulator Blocks |
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184 | (5) |
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4.4.2 Multiply ACcumulate |
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189 | (7) |
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196 | (5) |
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201 | (2) |
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4.6 Recommended Exercises |
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203 | (4) |
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5 Programmable Data Communication Blocks |
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207 | (36) |
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5.1 Abstract Communication Channels |
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208 | (4) |
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5.2 Channel Implementation Units |
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212 | (2) |
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5.3 Hardware-Software Implementation of Channels |
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214 | (5) |
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5.4 Channel Implementation Unit: SPI Block |
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219 | (10) |
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220 | (6) |
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226 | (3) |
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5.5 Channel Implementation Unit: UART Block |
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229 | (9) |
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5.5.1 UART Hardware Circuit |
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230 | (4) |
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234 | (4) |
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238 | (1) |
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5.7 Recommended Exercises |
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239 | (4) |
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6 Continuous-Time, Analog Building Blocks |
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243 | (46) |
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6.1 Introduction to Operational Amplifiers |
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244 | (19) |
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244 | (1) |
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244 | (10) |
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6.1.3 OpAmp Macromodeling |
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254 | (9) |
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6.2 Continuous-Time Analog Building Blocks |
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263 | (13) |
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6.2.1 Inverting Amplifiers |
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263 | (7) |
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6.2.2 Non-Inverting Amplifier |
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270 | (1) |
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271 | (1) |
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6.2.4 Difference Amplifier |
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272 | (1) |
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272 | (3) |
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275 | (1) |
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6.3 Reconfigurable Continuous-Time Analog Blocks |
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276 | (7) |
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283 | (2) |
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6.5 Recommended Exercises |
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285 | (4) |
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7 Switched-Capacitor Blocks |
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289 | (36) |
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7.1 Introduction to Switched Capacitor Techniques |
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290 | (5) |
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7.1.1 Nonidealities in Switched Capacitor Circuits |
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291 | (4) |
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7.2 Active Switched Capacitor Circuits |
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295 | (11) |
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7.2.1 Fixed Gain Amplifier |
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295 | (4) |
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299 | (1) |
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7.2.3 Switched Capacitor Integrator |
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300 | (2) |
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7.2.4 Switched Capacitor Differentiator |
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302 | (1) |
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7.2.5 Reference Selection |
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303 | (2) |
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7.2.6 Analog-to-Digital Conversion |
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305 | (1) |
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7.3 Switched Capacitor PSoC Blocks |
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306 | (14) |
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7.3.1 Type C Switched Capacitor Blocks |
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307 | (4) |
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7.3.2 Type D Switched Capacitor Blocks |
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311 | (9) |
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320 | (2) |
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7.5 Recommended Exercises |
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322 | (3) |
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8 Analog and Digital Filters |
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325 | (48) |
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326 | (6) |
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327 | (1) |
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8.1.2 Linear Active Filters |
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328 | (2) |
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330 | (1) |
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331 | (1) |
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332 | (12) |
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8.2.1 Specific Filter Types |
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334 | (4) |
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338 | (1) |
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8.2.3 Scaling and Normalization |
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339 | (1) |
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8.2.4 Cascading Analog Filters |
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340 | (4) |
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344 | (13) |
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8.3.1 Time-Continuous Integrators as Filters |
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344 | (2) |
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8.3.2 The Passive Lowpass Filter |
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346 | (3) |
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8.3.3 The Sallen-Key Lowpass Active Filter |
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349 | (2) |
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8.3.4 The Switched-Capacitance Filter |
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351 | (1) |
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8.3.5 Biquad Switched Capacitor Filter |
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352 | (3) |
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355 | (2) |
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357 | (8) |
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359 | (3) |
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8.4.2 Infinite Impulse Response Filter |
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362 | (3) |
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8.5 Filter Design Software Tools |
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365 | (1) |
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366 | (1) |
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8.7 Recommended Exercises |
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367 | (6) |
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9 ΔΣ Analog-to-Digital Converters |
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373 | (40) |
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9.1 Nyquist ADCs-A Short Introduction |
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374 | (5) |
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9.1.1 Sampling and Quantization |
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374 | (1) |
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374 | (4) |
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378 | (1) |
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379 | (30) |
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9.2.1 Oversampling and Noise-Shaping |
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380 | (1) |
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381 | (2) |
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9.2.3 First-Order ΔΣ Modulator |
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383 | (4) |
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9.2.4 PSoC Implementation of First-Order ΔΣ Modulators |
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387 | (7) |
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9.2.5 Impact of Circuit Non-Idealities on ΔΣ Modulator Performance |
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394 | (11) |
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9.2.6 Second-Order ΔΣ Modulator |
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405 | (4) |
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409 | (4) |
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10 Future Directions in Mixed-Signal Design Automation |
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413 | |
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10.1 Top-Down Design and Design Activities |
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413 | (2) |
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10.2 Two Examples of Architecture Customization |
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415 | (6) |
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10.2.1 IDEA Algorithm for Data Encryption |
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415 | (2) |
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10.2.2 Face Detection for Image Processing |
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417 | (4) |
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10.3 Challenges in Mixed-Signal Design Automation |
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421 | |
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10.3.1 High-Level Specification of Analog and Mixed-Signal Systems |
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422 | (2) |
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10.3.2 Fast Performance Estimation by Customized Simulation Code |
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424 | (11) |
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10.3.3 High-Level Synthesis of Analog Subsystems |
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435 | |
Index |
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443 | |