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LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers 2005 [Minkštas viršelis]

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LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers fits in the quest for complete CMOS integration of wireless receiver front-ends. With a combined discussion of both RF and ESD performance, it tackles one of the final obstacles on the road to CMOS integration. The book is conceived as a design guide for those actively involved in the design of CMOS wireless receivers.



The book starts with a comprehensive introduction to the performance requirements of low-noise amplifiers in wireless receivers. Several popular topologies are explained and compared with respect to future technology and frequency scaling. The ESD requirements are introduced and related to the state-of-the-art protection devices and circuits.



LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers provides an extensive theoretical treatment of the performance of CMOS low-noise amplifiers in the presence of ESD-protection circuitry. The influence of the ESD-protection parasitics on noise figure, gain, linearity, and matching are investigated. Several RF-ESD co-design solutions are discussed allowing both high RF-performance and good ESD-immunity for frequencies up to and beyond 5 GHz. Special attention is also paid to the layout of both active and passive components.







LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers offers the reader intuitive insight in the LNAs behavior, as well as the necessary mathematical background to optimize its performance. All material is experimentally verified with several CMOS implementations, among which a fully integrated GPS receiver front-end. The book is essential reading for RF design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.
Abstract ix
List of Symbols and Abbreviations
xi
1 Introduction
1(8)
1.1 The Growth of the Wireless Communication Market
1(2)
1.2 Evolution to CMOS RF
3(2)
1.3 CMOS, RF and ESD
5(1)
1.4 Outline of this Book
6(3)
2 Low-Noise Amplifiers in CMOS Wireless Receivers
9(46)
2.1 Introduction
9(1)
2.2 Some Important RF Concepts
9(8)
2.2.1 Quality Factor of Reactive Elements and Series-Parallel Transformation
9(2)
2.2.2 SNR and Noise Figure
11(1)
2.2.3 Impedance Matching, Power Matching, Noise Matching
12(1)
2.2.4 Transducer Power Gain, Operating Power Gain and Available Power Gain
13(2)
2.2.5 Intermodulation Distortion
15(2)
2.3 The Deep Sub-Micron MOS Transistor at Radio Frequencies
17(5)
2.3.1 MOS Model for Hand Calculations
17(1)
2.3.2 Linearity of the short-channel MOS transistor
18(1)
2.3.3 Non-Quasi Static Model
19(2)
2.3.4 Extended MOS Model for Simulation
21(1)
2.4 The Origin of Noise
22(3)
2.4.1 Resistor Thermal Noise
22(1)
2.4.2 Thermal Noise in MOS transistors
22(1)
2.4.2.1 Classical MOS Channel Noise
22(1)
2.4.2.2 Induced Gate Noise
23(1)
2.4.3 1/f Noise
24(1)
2.4.4 Shot Noise
24(1)
2.5 The LNA in the Receiver Chain
25(8)
2.5.1 Cascading Non-Ideal Building Blocks
25(1)
2.5.1.1 Noise in a Cascade
25(1)
2.5.1.2 IIV3 of a Cascade
26(1)
2.5.2 Wireless Receiver Architectures
27(1)
2.5.3 LNA Requirements
28(1)
2.5.3.1 Matching
28(1)
2.5.3.2 Noise Figure
29(1)
2.5.3.3 Voltage Gain or Power Gain
29(2)
2.5.3.4 Intermodulation Distortion
31(1)
2.5.3.5 Reverse Isolation
31(1)
2.5.3.6 Stability
32(1)
2.5.3.7 Single-ended vs. Differential
32(1)
2.6 Topologies for Low-Noise Amplifiers
33(21)
2.6.1 The Inductively Degenerated Common Source LNA
33(1)
2.6.1.1 From Basic Common-Source Amplifier to Inductively Degenerated Common-Source LNA
33(4)
2.6.1.2 Power Gain
37(2)
2.6.1.3 Noise Figure
39(3)
2.6.1.4 Linearity
42(1)
2.6.2 The Common-Gate LNA
43(1)
2.6.2.1 Input Matching
44(2)
2.6.2.2 Power Gain
46(1)
2.6.2.3 Noise Figure
46(1)
2.6.2.4 Linearity
47(1)
2.6.3 Shunt-Feedback Amplifier
48(2)
2.6.4 Image Reject LNA's
50(1)
2.6.5 Highly Linear Feedforward LNA
51(1)
2.6.6 The Noise-Cancelling Wide-band LNA
52(1)
2.6.7 Current Reuse LNA with Interstage Resonance
52(1)
2.6.8 Transformer Feedback LNA
53(1)
2.7 Conclusion
54(1)
3 ESD Protection in CMOS
55(18)
3.1 Introduction
55(1)
3.2 ESD Tests and Standards
56(6)
3.2.1 Human Body Model
56(1)
3.2.2 Machine Model
57(1)
3.2.3 Charged Device Model
58(1)
3.2.4 Transmission Line Pulsing
59(3)
3.3 ESD-Protection in CMOS
62(10)
3.3.1 ESD-Protection Devices
62(1)
3.3.1.1 Diode
62(1)
3.3.1.2 Grounded-Gate NMOS
63(3)
3.3.1.3 Gate-Coupled NMOS
66(1)
3.3.1.4 Silicon-Controlled Rectifier
66(2)
3.3.2 ESD-Protection Topologies
68(1)
3.3.2.1 I/O Pins
68(1)
3.3.2.2 Power Supply Clamping
69(3)
3.4 Conclusion
72(1)
4 Detailed Study of the Common-Source LNA with Inductive Degeneration
73(38)
4.1 Introduction
73(1)
4.2 The Non-Quasi Static Gate Resistance
73(5)
4.2.1 Influence of rg,NQS on Zin, GT and IIP3
74(1)
4.2.2 Influence of rg,NQS on the Noise Figure
75(3)
4.3 Parasitic Input Capacitance
78(11)
4.3.1 Impact of Cp
79(1)
4.3.1.1 Influence of Cp on Input Matching
80(2)
4.3.1.2 Influence of Cp on Power Gain, Noise Figure and IIP3
82(3)
4.3.2 Impact of Cp Non-Linearity
85(3)
4.3.3 Impact of the Finite Q of Cp
88(1)
4.4 Miller Capacitance
89(2)
4.5 Optimization of the Cascode Transistor
91(1)
4.6 Output Capacitance Non-Linearity
92(3)
4.7 Impact of a Non-Zero S11
95(1)
4.8 Output Considerations
96(4)
4.8.1 Load Impedance Constraints
96(2)
4.8.2 Output Matching
98(2)
4.9 LNA Bandwidth
100(1)
4.10 Layout Aspects
101(4)
4.10.1 RF Bonding Pads
101(1)
4.10.2 On-Chip Inductors
102(1)
4.10.2.1 Modelling
102(1)
4.10.2.2 Patterned Ground Shields
103(1)
4.10.3 The Amplifying Transistor
104(1)
4.10.4 The Cascode Transistor
105(1)
4.11 The Common-Gate LNA Revisited
105(4)
4.12 Conclusion
109(2)
5 RF-ESD Co-Design for CMOS LNA's
111(22)
5.1 Introduction
111(1)
5.2 ESD-protection within an L-Type Matching Network
112(7)
5.2.1 Introduction
112(1)
5.2.2 General Performance
113(2)
5.2.3 Design and Layout of the ESD Protection Diodes
115(1)
5.2.4 Non-Linearity of Input ESD Protection Diodes
116(3)
5.2.5 Conclusion
119(1)
5.3 ESD-Protection within a Π-Type Matching Network
119(4)
5.4 Inductive ESD-Protection
123(3)
5.5 Comparison
126(2)
5.6 Other ESD-Protection Strategies
128(2)
5.6.1 Distributed ESD-Protection
128(2)
5.6.2 ESD-Protection with T-Coils
130(1)
5.7 ESD-Protection for the Common-Gate LNA
130(1)
5.8 Conclusion
130(3)
6 Integrated CMOS Low-Noise Amplifiers
133(38)
6.1 Introduction
133(1)
6.2 A 0.8 dB NF ESD-Protected 9 mW CMOS LNA
133(14)
6.2.1 The GPS Power Levels
133(1)
6.2.2 Topology
134(1)
6.2.3 Design
135(4)
6.2.4 Layout
139(2)
6.2.5 Experimental Results
141(3)
6.2.6 Discussion and Comparison
144(3)
6.2.7 Conclusion
147(1)
6.3 A 1.3 dB NF CMOS LNA for GPS with 3 kV HBM ESD-Protection
147(12)
6.3.1 The Complete GPS Receiver Front-End
147(1)
6.3.1.1 Architecture
147(1)
6.3.1.2 Low-Noise Amplifier
148(1)
6.3.1.3 Quadrature, Direct Digital Downconversion
148(1)
6.3.1.4 PLL Frequency Synthesizer
149(1)
6.3.2 The Low Noise Amplifier
150(3)
6.3.3 Results
153(5)
6.3.4 Conclusion
158(1)
6.4 A 5 GHz LNA with Inductive ESD-Protection Exceeding 3 kV HBM
159(10)
6.4.1 5 GHz Wireless LAN
159(1)
6.4.2 Design
160(5)
6.4.3 Results
165(4)
6.4.4 Conclusion
169(1)
6.5 Conclusion
169(2)
7 Conclusions
171(2)
A Fundamentals of Two-Port Noise Theory 173(2)
Index 175