Preface |
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xix | |
Foreword |
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xxi | |
Acknowledgments |
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xxv | |
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PART 1 PRINCIPLES OF MODERN EMBEDDED SYSTEMS |
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Chapter 1 Embedded Systems Landscape |
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3 | (6) |
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What Is an Embedded Computer System? |
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3 | (2) |
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Applications and Form Factors |
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4 | (1) |
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4 | (1) |
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System Resources and Features |
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5 | (1) |
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5 | (1) |
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Why Is This Transition Inevitable? |
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5 | (2) |
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What Range of Embedded Systems Exists? |
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7 | (1) |
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What to Expect from the Rest of This Book |
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8 | (1) |
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Chapter 2 Attributes of Embedded Systems |
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9 | (14) |
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Embedded Platform Characteristics |
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12 | (9) |
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Central Processing Unit (CPU) |
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12 | (1) |
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13 | (1) |
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14 | (1) |
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15 | (2) |
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17 | (1) |
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Application-Specific Hardware |
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17 | (1) |
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18 | (1) |
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18 | (1) |
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19 | (1) |
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20 | (1) |
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20 | (1) |
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21 | (2) |
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Chapter 3 The Future of Embedded Systems |
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23 | (18) |
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23 | (7) |
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24 | (1) |
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25 | (4) |
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29 | (1) |
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30 | (1) |
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Issues, Applications, and Initiatives |
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30 | (4) |
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30 | (2) |
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32 | (1) |
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33 | (1) |
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Challenges and Uncertainties |
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34 | (2) |
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Open Systems, Internet Access, and Neutrality |
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34 | (1) |
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35 | (1) |
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Successful Commercialization |
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36 | (1) |
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36 | (5) |
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PART 2 EMBEDDED SYSTEMS ARCHITECTURE AND OPERATION |
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Chapter 4 Embedded Platform Architecture |
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41 | (58) |
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41 | (20) |
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41 | (2) |
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43 | (1) |
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44 | (11) |
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55 | (6) |
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Volatile Memory Technologies |
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61 | (6) |
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62 | (4) |
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66 | (1) |
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67 | (6) |
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68 | (2) |
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70 | (2) |
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Hard Disk Drives and Solid State Drives |
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72 | (1) |
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Device Interface---High Performance |
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73 | (7) |
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Peripheral Component Interconnect (PCI) |
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74 | (6) |
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80 | (9) |
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85 | (4) |
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89 | (1) |
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Device Interconnect---Low Performance |
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89 | (7) |
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Inter-Integrated Circuit Bus |
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89 | (2) |
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System Management Bus (SMBus) |
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91 | (1) |
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Serial Peripheral Interface (SPI) |
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92 | (1) |
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93 | (1) |
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93 | (1) |
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Universal Asynchronous Receiver/Transmitter |
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93 | (3) |
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General-Purpose Input/Output |
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96 | (1) |
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97 | (1) |
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97 | (2) |
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Chapter 5 Embedded Processor Architecture |
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99 | (54) |
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Basic Execution Environment |
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99 | (8) |
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103 | (1) |
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104 | (1) |
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105 | (2) |
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Application Binary Interface |
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107 | (5) |
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Processor Instruction Classes |
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112 | (9) |
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113 | (1) |
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113 | (1) |
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114 | (1) |
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Data Transfer Instructions |
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114 | (1) |
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115 | (3) |
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Branch and Control Flow Instructions |
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118 | (1) |
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Structure/Procedure Instructions |
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119 | (1) |
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120 | (1) |
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Exceptions/Interrupts Model |
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121 | (3) |
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Precise and Imprecise Exceptions |
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122 | (2) |
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124 | (2) |
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126 | (1) |
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126 | (2) |
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128 | (1) |
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128 | (2) |
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Memory Mapping and Protection |
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130 | (1) |
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131 | (4) |
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135 | (1) |
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135 | (1) |
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136 | (9) |
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138 | (1) |
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138 | (4) |
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142 | (3) |
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145 | (1) |
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145 | (1) |
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Intel Atom Microarchitecture (Supplemental Material) |
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145 | (8) |
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146 | (3) |
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149 | (2) |
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151 | (1) |
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152 | (1) |
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Chapter 6 Embedded Platform Boot Sequence |
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153 | (26) |
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Multi-Core and Multi-Processor Boot |
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153 | (1) |
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Boot Technology Considerations |
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154 | (2) |
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Hardware Power Sequences (the Pre-Pre-Boot) |
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156 | (1) |
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Reset: The First Few Steps and a Jump |
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157 | (2) |
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159 | (4) |
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159 | (1) |
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159 | (2) |
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161 | (1) |
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161 | (1) |
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162 | (1) |
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163 | (1) |
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AP Processor Initialization |
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163 | (1) |
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164 | (5) |
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General-Purpose Input/Output |
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164 | (1) |
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164 | (1) |
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165 | (1) |
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165 | (1) |
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166 | (1) |
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166 | (1) |
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167 | (1) |
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167 | (1) |
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168 | (1) |
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168 | (1) |
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168 | (1) |
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168 | (1) |
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Legacy BIOS and UEFI Framework Software |
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169 | (7) |
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Legacy Operating System Boot |
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169 | (4) |
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Extensible Firmware Interface |
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173 | (3) |
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176 | (1) |
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177 | (2) |
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Chapter 7 Operating Systems Overview |
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179 | (48) |
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179 | (2) |
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179 | (1) |
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180 | (1) |
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Processes, Tasks, and Threads |
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181 | (5) |
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184 | (1) |
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Task State and State Transitions |
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184 | (2) |
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186 | (5) |
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186 | (1) |
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Round-Robin Scheduler with Priority and Preemption |
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187 | (2) |
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189 | (1) |
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POSIX-Compliant Scheduler |
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190 | (1) |
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191 | (4) |
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Virtual Memory and Protection |
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193 | (2) |
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195 | (1) |
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195 | (1) |
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195 | (2) |
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195 | (1) |
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196 | (1) |
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197 | (1) |
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Mutual Exclusion/Synchronization |
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197 | (5) |
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202 | (10) |
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207 | (2) |
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209 | (1) |
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210 | (2) |
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212 | (1) |
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213 | (3) |
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215 | (1) |
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215 | (1) |
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216 | (1) |
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216 | (3) |
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218 | (1) |
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219 | (1) |
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219 | (2) |
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221 | (3) |
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Device Interrupt Delivery |
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221 | (1) |
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Processor Interrupt Handler |
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222 | (1) |
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222 | (1) |
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223 | (1) |
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224 | (3) |
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227 | (42) |
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227 | (4) |
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228 | (1) |
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229 | (2) |
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Anatomy of an Embedded Linux |
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231 | (3) |
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234 | (12) |
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234 | (2) |
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236 | (3) |
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239 | (3) |
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242 | (1) |
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243 | (1) |
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244 | (2) |
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246 | (3) |
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246 | (1) |
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247 | (2) |
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249 | (13) |
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250 | (6) |
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256 | (2) |
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258 | (4) |
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262 | (5) |
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262 | (1) |
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Access to User Space Memory from the Kernel |
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262 | (1) |
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263 | (1) |
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264 | (1) |
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265 | (1) |
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PCI Memory Allocation and Mapping |
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265 | (2) |
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267 | (1) |
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267 | (1) |
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267 | (1) |
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268 | (1) |
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268 | (1) |
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Chapter 9 Power Optimization |
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269 | (22) |
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269 | (1) |
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The Power Profile of an Embedded Computing System |
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270 | (1) |
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Constant Versus Dynamic Power |
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271 | (2) |
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271 | (1) |
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271 | (2) |
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A Simple Model of Power Efficiency |
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273 | (2) |
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Advanced Configuration and Power Interface (ACPI) |
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275 | (6) |
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277 | (1) |
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277 | (1) |
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Global System States (Gx States) |
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278 | (1) |
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278 | (1) |
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Device Power States (Dx States) |
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279 | (1) |
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Processor Power States (Cx States) |
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280 | (1) |
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Processor Performance States (Px States) |
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280 | (1) |
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Enhanced Intel SpeedStep Technology |
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281 | (1) |
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Optimizing Software for Power Performance |
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281 | (8) |
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281 | (1) |
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282 | (1) |
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282 | (2) |
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Using PowerTOP to Evaluate Software and Systems |
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284 | (5) |
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289 | (2) |
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Chapter 10 Embedded Graphics and Multimedia Acceleration |
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291 | (26) |
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293 | (4) |
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293 | (3) |
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296 | (1) |
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296 | (1) |
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297 | (2) |
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299 | (1) |
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299 | (1) |
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299 | (2) |
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301 | (3) |
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303 | (1) |
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Video Capture and Encoding |
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304 | (6) |
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304 | (6) |
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310 | (5) |
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310 | (3) |
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313 | (2) |
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315 | (1) |
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315 | (2) |
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Chapter 11 Digital Signal Processing Using General-Purpose Processors |
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317 | (30) |
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318 | (6) |
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318 | (1) |
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319 | (2) |
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321 | (1) |
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Fixed-Point and Floating-Point Implementations |
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322 | (2) |
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Single Instruction Multiple Data |
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324 | (1) |
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SIMD Microarchitecture and Instructions |
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324 | (1) |
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324 | (1) |
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Microarchitecture Considerations |
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325 | (1) |
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325 | (1) |
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Intrinsics and Data Types |
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326 | (2) |
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328 | (3) |
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331 | (1) |
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Finite Impulse Response Filter |
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332 | (5) |
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333 | (1) |
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FIR Example: Intel Performance Primitives |
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333 | (1) |
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334 | (3) |
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337 | (9) |
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337 | (2) |
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Medical Ultrasound Imaging |
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339 | (5) |
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344 | (2) |
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346 | (1) |
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Chapter 12 Network Connectivity |
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347 | (32) |
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349 | (4) |
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Layering and Network Software |
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349 | (1) |
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Node Operation and Network Hardware |
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350 | (1) |
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Sockets and a Simple Example |
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351 | (2) |
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353 | (8) |
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Governance, the IETF, and RFCs |
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354 | (1) |
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Addresses, Packets, and Routes |
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355 | (4) |
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Port Numbers, Byte Ordering, and OS Tools |
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359 | (1) |
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Supporting Protocols and Services |
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360 | (1) |
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361 | (4) |
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361 | (1) |
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362 | (1) |
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363 | (1) |
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363 | (1) |
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A Gigabit Ethernet Controller and Its Features |
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364 | (1) |
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365 | (4) |
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366 | (1) |
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366 | (1) |
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367 | (1) |
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A Wi-Fi Adapter and Its Features |
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368 | (1) |
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369 | (3) |
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369 | (1) |
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369 | (1) |
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370 | (2) |
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372 | (6) |
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Tools and Monitor and Control Network Interfaces and Sockets |
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372 | (1) |
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372 | (4) |
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Linux Kernel Networking Structures |
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376 | (2) |
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378 | (1) |
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Chapter 13 Application Frameworks |
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379 | (18) |
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379 | (1) |
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379 | (13) |
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Android Framework Architecture |
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381 | (3) |
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Android Application Architecture |
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384 | (5) |
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Android Development Environment |
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389 | (2) |
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391 | (1) |
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392 | (2) |
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Qt Application Development Framework |
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392 | (2) |
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394 | (1) |
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394 | (1) |
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395 | (1) |
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395 | (2) |
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Chapter 14 Platform and Content Security |
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397 | (26) |
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398 | (4) |
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Confidentiality, Integrity, and Availability (CIA) |
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400 | (2) |
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Security Concepts and Building Blocks |
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402 | (18) |
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Encryption and Cryptography |
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402 | (2) |
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Secure Web Communications: TLS |
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404 | (3) |
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407 | (1) |
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Security Architecture for IP: IPSec |
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408 | (3) |
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Two-Factor Authentication |
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411 | (1) |
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Major Categories of Security Attacks |
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411 | (5) |
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416 | (3) |
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419 | (1) |
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Platform Support for Security |
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420 | (1) |
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421 | (2) |
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Chapter 15 Advanced Topics: SMP, AMP, and Virtualization |
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423 | (22) |
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424 | (9) |
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424 | (4) |
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428 | (4) |
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Physical versus Logical Cores |
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432 | (1) |
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Impact on Systems and Software |
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432 | (1) |
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Symmetric Multiprocessing |
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433 | (2) |
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433 | (1) |
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433 | (2) |
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Interprocess Communication |
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435 | (1) |
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Asymmetric Multiprocessing |
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435 | (2) |
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436 | (1) |
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436 | (1) |
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437 | (1) |
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437 | (1) |
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437 | (1) |
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Methods for Platform Virtualization |
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438 | (4) |
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438 | (1) |
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Hardware Support for Virtualization |
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439 | (1) |
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439 | (1) |
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439 | (1) |
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440 | (2) |
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442 | (3) |
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PART 3 DEVELOPING AN EMBEDDED SYSTEM |
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Chapter 16 Example Designs |
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445 | (20) |
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Intel Atom E6XX Series Platforms |
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445 | (7) |
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446 | (2) |
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Platform Controller Hub(s) |
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448 | (4) |
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Multi-Radio Communications Design |
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452 | (6) |
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452 | (3) |
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455 | (3) |
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458 | (5) |
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458 | (1) |
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459 | (4) |
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463 | (1) |
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464 | (1) |
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Chapter 17 Platform Debug |
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465 | (12) |
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465 | (1) |
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A Process for Debugging a New Platform |
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466 | (1) |
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Debug Tools and Chipset Features |
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467 | (2) |
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468 | (1) |
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468 | (1) |
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468 | (1) |
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Power-On Self-Test (POST) Cards |
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468 | (1) |
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469 | (1) |
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469 | (5) |
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469 | (1) |
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470 | (4) |
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474 | (1) |
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474 | (1) |
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475 | (2) |
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Chapter 18 Performance Tuning |
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477 | (20) |
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477 | (1) |
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478 | (5) |
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Defined Performance Requirement |
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478 | (1) |
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478 | (1) |
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Premature Code Tuning Avoided |
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479 | (1) |
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479 | (1) |
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480 | (1) |
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Best Compiler for Application |
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480 | (1) |
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481 | (1) |
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482 | (1) |
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483 | (5) |
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483 | (1) |
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Supersonic Interrupt Service Routines |
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483 | (1) |
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Assembly-Language-Critical Functions |
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484 | (1) |
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484 | (1) |
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484 | (1) |
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Minimizing Local Variables |
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485 | (1) |
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485 | (1) |
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Optimized Hardware Register Use |
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485 | (1) |
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Avoiding the OS Buffer Pool |
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486 | (1) |
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486 | (1) |
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Disabled Counters/Statistics |
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487 | (1) |
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488 | (4) |
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488 | (1) |
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488 | (1) |
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489 | (1) |
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Separate DRAM Memory Banks |
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489 | (1) |
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490 | (1) |
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490 | (1) |
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Cache-Aligned Data Buffers |
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491 | (1) |
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491 | (1) |
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491 | (1) |
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492 | (1) |
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492 | (5) |
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492 | (1) |
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Evaluating Traffic Generator and Protocols |
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493 | (1) |
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494 | (3) |
References |
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497 | (6) |
Index |
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503 | |