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El. knyga: Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges

Edited by (Ecole Polytechnique de Montréal, Canada), Edited by (Hong Kong University of Science and Technology, China), Edited by (Ecole Centrale de Lyon, France), Edited by (Ecole Polytechnique de Montréal, Canada)
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In recent years, there has been a considerable amount of effort in both industry and academia that focuses on the design, implementation, performance analysis, evaluation, and prediction of silicon photonic interconnects for inter- and intra-chip communication, paving a way for the next and future generation of high-performance computing systems’ design and dimensioning. Photonic Interconnects for Computing Systems provides a comprehensive overview of the current state-of-the-art technology and research achievements in employing silicon photonics for interconnection networks and high-performance computing, summarizing main opportunities and some challenges. The majority of the chapters were collected from presentations made at the International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS) held over the past two years. The workshop invites internationally recognized speakers on the range of topics relevant to silicon photonics and computing systems.

Technical topics discussed in the book include:
- Design and Implementation of Chip-Scale Photonic Interconnects
- Developing Design Automation Solutions for Chip-Scale Photonic Interconnects
- Design Space Exploration in Chip-Scale Photonic Interconnects
- Thermal Analysis and Modeling in Photonic Interconnects
- Design for Reliability
- Fabrication Non-Uniformity in Photonic Interconnects

Photonic Interconnects for Computing Systems presents a compilation of outstanding contributions from leading research groups in the field. It presents a comprehensive overview of the design, advantages, challenges, and requirements of photonic interconnects for computing systems. The selected contributions present important discussions and approaches related to the design and development of novel photonic interconnect architectures as well as various design solutions to improve the performance of such systems while considering different challenges. The book is ideal for personnel in computer/photonic industries as well as academic staff and master/graduate students in computer science and engineering, electronic engineering, electrical engineering, and photonics.
List of Contributors xv
List of Figures xix
List of Tables xxxv
List of Abbreviations xxxvii
Introduction 1(10)
Mandi Nikdast
Gabriela Nicolescu
Sebastien Le Beux
Jiang Xu
Part I: Design, Application and Implementation
1 Unified Inter- and Intra-chip Optical Interconnect Networks
11(30)
Peng Yang
Xiaowen Wu
Yaoyao Ye
Jiang Xu
1.1 Introduction
11(3)
1.2 Related Work
14(3)
1.3 Architecture Overview
17(2)
1.4 Intra-chip Network Design
19(8)
1.4.1 Data Channel Design
21(1)
1.4.1.1 Optical network interface
21(1)
1.4.1.2 Optical transceiver
22(1)
1.4.1.3 Channel segmentation
23(1)
1.4.2 Control Subsystem
24(1)
1.4.2.1 Channel partition
25(1)
1.4.2.2 Node agent design
26(1)
1.5 Inter-chip Network Design
27(4)
1.5.1 Inter-chip Data Channel
28(1)
1.5.2 Control Subsystem
29(2)
1.6 Evaluations
31(6)
1.6.1 Node Agent Power and Area
32(2)
1.6.2 Performance
34(1)
1.6.3 Energy Efficiency
35(2)
1.7 Conclusion
37(1)
References
37(4)
2 Design and Optimization of Vertical Interconnections for Multilayer Optical Networks-on-Chip
41(32)
Alberto Parini
Gaetano Bellanca
2.1 Introduction
41(3)
2.2 Materials for Photonic Integrated Circuit Fabrication
44(2)
2.3 Technological Platforms for Multilayer Photonics
46(3)
2.4 Overview of Vertical Interconnection Schemes
49(3)
2.5 Isolation between Layers in Vertical Stacked Structures
52(3)
2.6 Design Space Exploration of Inverse Tapered Couplers
55(6)
2.7 Design of MMI-based Vertical Links
61(4)
2.8 Concluding Remarks
65(3)
Acknowledgments
68(1)
References
68(5)
3 Optical Interconnection Networks: The Need for Low-Latency Controllers
73(34)
Felipe Gohring de Magalhaes
Mandi Nikdast
Fabiano Hessel
Odile Liboiron-Ladouceur
Gabriela Nicolescu
3.1 Introduction
74(1)
3.2 Control Strategies
75(5)
3.2.1 Time Sharing
76(2)
3.2.2 Circuit-Switching
78(1)
3.2.3 Wavelength Division
79(1)
3.3 Low-Latency Controlling Solution for OINs
80(7)
3.4 Results
87(10)
3.5 State of the Art
97(5)
3.6 Conclusion
102(1)
References
102(5)
4 Interconnects and Data System Throughput
107(30)
Keyon Janani
Sakshi Singh
Moustafa Mohamed
Alan Mickelson
4.1 Introduction
107(2)
4.2 Interconnections
109(5)
4.2.1 Electrical and Optical Interconnections
110(1)
4.2.1.1 Electrical interconnections
111(1)
4.2.1.2 Optical interconnections
113(1)
4.3 Photonic Transceivers
114(3)
4.4 Data Centers
117(5)
4.4.1 Energy Use
117(1)
4.4.2 Folded Clos (Leaf-Spine) Architecture
117(2)
4.4.3 Hierarchy of Interconnection
119(1)
4.4.4 Electrical Switching
120(1)
4.4.5 Electrical versus Optical
120(2)
4.5 Modeling of Optically Connected Data Centers
122(4)
4.5.1 Data Center Modeling
123(1)
4.5.2 Optics in Data Center Simulation
124(2)
4.6 Disaggregation
126(2)
4.7 Discussion
128(1)
4.8 Conclusion
128(1)
References
129(8)
Part II: Developing Design Automation Solutions and Enabling Design Exploration
5 Design Automation Beyond Its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip
137(34)
Marta Ortin-Obon
Andrea Peano
Mandi Tala
Marco Balboni
Luca Ramini
Maddalena Nonato
Victor Vifials-Yufera
Davide Bertozzi
5.1 Introduction
137(2)
5.2 Analogy with EDA Flows
139(3)
5.3 Wavelength-Selective Routing
142(3)
5.4 WRONoC Synthesis Methodology at a Glance
145(1)
5.5 Front-End Synthesis Methodology
146(4)
5.5.1 Wavelength Resolution
147(1)
5.5.2 Technology Mapping
148(1)
5.5.3 Symbolic Wavelength Assignment
149(1)
5.5.4 Topology Connection
150(1)
5.6 Device Parameter Selection
150(6)
5.6.1 The Routing Fault Concern
151(2)
5.6.2 The Role of Parameter Uncertainty
153(2)
5.6.3 Problem Formulation: A Case Study
155(1)
5.7 Physical Mapping Flow
156(3)
5.8 Experimental Results
159(7)
5.8.1 Synthesis of Logical Topologies
159(2)
5.8.2 The Design Predictability Gap
161(2)
5.8.3 Bounds on Connectivity and Parallelism
163(3)
5.9 Conclusions
166(1)
References
166(5)
6 Application-Specific Mapping Optimizations for Photonic Networks-on-Chip
171(20)
Edoardo Fusella
Alessandro Cilardo
Jose Flich
6.1 Introduction
171(1)
6.2 Motivation: Application-Specific Mapping Optimization
172(2)
6.3 Architecture Description
174(6)
6.3.1 Architecture Overview
175(1)
6.3.2 The Photonic Switch Element Model
176(2)
6.3.3 The Router Model
178(2)
6.4 Methodology
180(5)
6.4.1 Problem Formulation
180(1)
6.4.2 Genetic Algorithm
181(4)
6.5 Results
185(2)
6.6 Conclusion
187(1)
References
188(3)
7 Integrated Photonics for Chip-Multiprocessor Architectures
191(36)
Sandro Bartolini
Paolo Grani
7.1 Introduction
191(1)
7.2 Tiled Architectures and Networks on Chip
192(3)
7.2.1 Limits of Electronic Wires and Benefits of Silicon Photonics from the Architectural Viewpoint
193(2)
7.3 Coherence Protocols
195(2)
7.4 Experimental Methodology
197(2)
7.4.1 Simulator
197(1)
7.4.2 Benchmarks
198(1)
7.5 Passive Optical Networks for CMPs
199(7)
7.5.1 Analyzed Architecture
200(1)
7.5.2 Arbitration Strategies and Physical Layout Implications
201(2)
7.5.3 Results
203(3)
7.6 Optical Dynamic Reconfigurable Networks for CMPs
206(9)
7.6.1 Background on Circuit Switched Optical NoCs
206(1)
7.6.2 Limitations of Existing Solutions
207(3)
7.6.3 Analyzed Architecture
210(1)
7.6.3.1 Logical operating scheme
211(2)
7.6.4 Results
213(2)
7.7 Conclusions
215(1)
References
216(11)
Part III: Challenges in Performance Analysis and Design Solutions
8 Thermal Management of Silicon Photonic NoCs in Many-core Systems
227(22)
Tiansheng Zhang
Jonathan Klamkin
Ajay Joshi
Ayse K. Coskun
8.1 Introduction
228(1)
8.2 Thermal Sensitivity of Optical Devices in PNoCs
229(3)
8.3 Design Methods for Thermal Management in PNoCs
232(7)
8.3.1 Device-level Techniques
232(2)
8.3.2 Chip-level Techniques
234(5)
8.4 Runtime Methods for Thermal Management in PNoCs
239(5)
8.5 Conclusion
244(1)
Acknowledgement
245(1)
References
245(4)
9 Thermal-Aware Design Method for On-Chip Laser-based Optical Interconnect
249(32)
Hui Li
Alain Fourmigue
Sdbastien Le Beux
Xavier Letartre
Ian O'Connor
Gabriela Nicolescu
9.1 Introduction
249(2)
9.2 Related Work
251(2)
9.3 3D Architecture
253(5)
9.3.1 Architecture Overview
253(1)
9.3.2 ONoC Interface and Thermal Sensitivity
254(1)
9.3.3 CMOS-Compatible On-Chip Lasers
255(3)
9.3.4 Contribution
258(1)
9.4 Proposed Design Methodology
258(8)
9.4.1 Design Methodology Overview
258(1)
9.4.2 Thermal Analysis
259(2)
9.4.3 SNR Analysis
261(1)
9.4.3.1 SNR model
261(1)
9.4.3.2 Signal attenuation and crosstalk
261(1)
9.4.3.3 Transmission principles of MR
263(3)
9.5 Case Study
266(5)
9.5.1 System Specification
266(1)
9.5.1.1 SCC and package
266(1)
9.5.1.2 ORNoC
267(2)
9.5.2 SNR Analysis in the Considered Architecture
269(2)
9.5.3 Thermal Characteristics of On-Chip Laser
271(1)
9.6 Results
271(5)
9.6.1 Reduction of the ONI Gradient Temperature
272(2)
9.6.2 System Level Estimation of SNR
274(2)
9.7 Conclusion
276(1)
Acknowledgement
276(1)
References
276(5)
10 Fault-tolerant Photonic Network-on-Chip
281(38)
Michael Meyer
Abderazek Ben Abdallah
10.1 Introduction
281(7)
10.1.1 Design Challenges
282(2)
10.1.2 Fault Models
284(1)
10.1.2.1 PNoC signal strength
284(1)
10.1.2.2 Electrostatic discharge
284(1)
10.1.2.3 Noise
285(1)
10.1.2.4 Aging
285(1)
10.1.2.5 Process variability
286(1)
10.1.2.6 Temperature variation
286(2)
10.2 Fault-tolerant Photonic Network-on-Chip Architecture
288(12)
10.2.1 Microring Fault-resilient Photonic Router
288(6)
10.2.2 Light-weight Electronic Control Router
294(1)
10.2.3 Fault-tolerant Path-configuration and Routing
294(6)
10.3 Evaluation
300(7)
10.3.1 Complexity Evaluation
301(1)
10.3.2 Latency and Bandwidth Evaluation
302(3)
10.3.3 Energy Evaluation
305(2)
10.4 Related Literature
307(3)
10.5
Chapter Summary and Discussion
310(1)
References
311(8)
11 Techniques for Energy Proportionality in Optical Interconnects
319(36)
Yigit Demir
Nikos Hardavellas
11.1 Laser Power-Gating
320(15)
11.1.1 Why Lasers Waste Power
320(1)
11.1.2 The Solution: Laser Power-Gating
320(1)
11.1.3 Background
321(1)
11.1.3.1 Laser primer
321(1)
11.1.3.2 Nanophotonic interconnect topologies
323(1)
11.1.4 Laser Control Schemes
323(1)
11.1.4.1 Proactive laser control
324(1)
11.1.4.2 Controlling an off-chip laser source
326(1)
11.1.5 Experimental Methodology
327(1)
11.1.5.1 Interconnect modeling
327(1)
11.1.5.2 Modeling optical and electrical multicore NoC
328(1)
11.1.5.3 Laser power modeling
329(1)
11.1.5.4 Resonant ring heater modeling
331(1)
11.1.5.5 The overheads of laser control
331(1)
11.1.6 Experimental Results
332(1)
11.1.7 Case Study 1: Radix-16 R-SWMR
333(1)
11.1.8 Case Study 2: Firefly
333(1)
11.1.9 Related Work
334(1)
11.2 Minimizing Ring Trimming Power
335(8)
11.2.1 Introduction
335(1)
11.2.2 Solution: Photonic Die Insulation with Parka
336(1)
11.2.3 Experimental Methodology
337(1)
11.2.3.1 Modeling the Ring-Heater Power Consumption
337(1)
11.2.3.2 Modeling cooling solutions
328(1)
11.2.4 Experimental Results
328(1)
11.2.4.1 Impact on ring-heating power consumption
338(1)
11.2.4.2 Impact on a realistic multicore
341(2)
11.2.5 Related Work
343(1)
11.3 Future Work
343(1)
Acknowledgements
344(1)
References
344(11)
Part IV: On the Impact of Fabrication Non-Uniformity
12 Impact of Fabrication Non-Uniformity on Silicon Photonic Networks-on-Chip
355(30)
Mandi Nikdast
Gabriela Nicolescu
Jelena Trajkovic
Odile Liboiron-Ladouceur
12.1 Introduction
356(2)
12.2 Optical Waveguides and MR-Based Devices
358(7)
12.2.1 Strip Waveguides under Process Variations
359(2)
12.2.2 MR-Based Add-Drop Filters and Switches under Process Variations
361(1)
12.2.2.1 Resonant wavelength shift in MRs
362(1)
12.2.3 Optical Spectra of MRs under Process Variations
363(2)
12.3 Optical Networks-on-Chip under Process Variations
365(4)
12.3.1 Process Variations in Optical Switches
365(2)
12.3.2 Process Variations at the System-Level in ONoCs
367(2)
12.4 Quantitative Simulation Results and Evaluations
369(8)
12.4.1 Simulation Results at the Component- and Device-level
370(5)
12.4.2 Simulation Results at the System-level
375(2)
12.5 Chip Fabrication and Measurement Results
377(4)
12.6 Conclusion
381(1)
References
381(4)
13 Enhancing Process Variation Resilience in Photonic NoC Architectures
385(22)
Sai Vineel Reddy Chittamuru
Ishan G. Thakkar
Sudeep Pasricha
13.1 Introduction
385(2)
13.2 Related Work
387(2)
13.3 Analytical Model for PV-Aware Crosstalk Analysis
389(6)
13.3.1 Impact of Localized Trimming on Crosstalk
389(2)
13.3.2 Crosstalk Modeling for Corona PNoC
391(3)
13.3.3 Modeling PV of MR Devices in Corona PNoC
394(1)
13.4 Double-Bit Crosstalk Mitigation (DBCTM)
395(3)
13.4.1 Overview
395(2)
13.4.2 DBCTM Sensitivity Analysis with Corona PNoC
397(1)
13.5 Experiments
398(6)
13.5.1 Experimental setup
398(1)
13.5.2 Experimental Results with Corona PNoC
399(5)
13.6 Conclusion
404(1)
References
404(3)
Index 407(4)
About the Editors 411
Gabriela Nicolescu, Mahdi Nikdast, Sébastien Le Beux
Daugiau apie elektronines knygas Daugiau apie elektronines knygas
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