VHDL Design Representation and Synthesis 2nd edition [Minkštas viršelis]

Preface		xi
Structured Design concepts		1	(16)
The Abstraction Hierarchy		1	(4)
Textual vs. Pictorial Representations		5	(2)
Types of Behavioral Descriptions		7	(1)
Design Process		8	(1)
Structural Design Decomposition		9	(2)
The Digital Design Space		11	(6)
Design Tools		17	(24)
CAD Tool Taxonomy		17	(2)
Editors		18	(1)
Simulators		18	(1)
Checkers and Analyzers		18	(1)
Optimizers and Synthesizers		18	(1)
Cad Systems		18	(1)
Schematic Editors		19	(3)
Simulators		22	(5)
Simulation Cycle		24	(1)
Simulator Organization		25	(1)
Language Scheduling Mechanism		25	(1)
Simulation Efficiency		25	(2)
The Simulation System		27	(1)
Simulation Aids		28	(4)
Model Preparation		28	(1)
Model Test Vector Development		29	(1)
Model Debugging		29	(2)
Results Interpretation		31	(1)
Applications of Simulation		32	(1)
Synthesis Tools		33	(8)
Basic Features of VHDL		41	(94)
Major Language Constructs		43	(8)
Design Entities		43	(1)
Architectural Bodies		44	(4)
Model Testing		48	(1)
Block Statements		49	(1)
Processes		50	(1)
Lexical Description		51	(6)
Character Set		52	(1)
Lexical Elements		52	(1)
Delimiters		53	(1)
Identifiers		53	(1)
Comments		54	(1)
Character Literal		55	(1)
String Literal		55	(1)
Bit String Literal		55	(1)
Abstract Literal		56	(1)
Decimal Literal		56	(1)
Based Literal		56	(1)
VHDL Source File		57	(1)
Data Types		57	(11)
Classification of Types		58	(1)
Scalar Data Types		58	(6)
Composite Data Types		64	(4)
Access Types		68	(1)
File Types		68	(1)
Type Marks		68	(1)
Data Objects		68	(4)
Classes of Objects		68	(1)
Declaration of Data Objects		69	(3)
Language Statements		72	(24)
Assignment Statements		72	(5)
Operators and Expressions		77	(6)
Sequential Control Statements		83	(3)
Architecture Declarations and Concurrent Statements		86	(4)
Subprograms		90	(6)
Advanced Features of VHDL		96	(18)
Overloading		96	(3)
Packages		99	(1)
Visibility		100	(3)
Libraries		103	(1)
Configurations		104	(3)
File I/O		107	(7)
The Formal Nature of VHDL		114	(1)
VHDL 93		115	(7)
Lexical Character Set		115	(1)
Syntax Changes		115	(1)
Process and Signal Timing and New Signal Attributes		116	(2)
New Operators		118	(1)
Improvements to Structural Models		118	(1)
Shared Variables		119	(1)
Improved Reporting Capability		120	(1)
General Programming Features		120	(1)
File I/O		121	(1)
Groups		122	(1)
Extension of Bit String Literals		122	(1)
Additions and Changes to Package Standard		122	(1)
Summary		122	(13)
Basic VHDL Modeling Techniques		135	(50)
Modeling Delay in VHDL		135	(12)
Propagation Delay		135	(3)
Delay and Concurrency		138	(2)
Sequential and Concurrent Statements in VHDL		140	(1)
Implementation of Time Delay in the VHDL Simulator		141	(5)
Inertial and Transport Delay in Signal Propagation		146	(1)
The VHDL Scheduling Algorithm		147	(3)
Waveform Updating		147	(3)
Side Effects		150	(1)
Modeling Combinational and Sequential Logic		150	(3)
Logic Primitives		153	(32)
Combinational Logic Primitives		153	(10)
SEQUENTIAL LOGIC		163	(5)
Testing Models: Test Bench Development		168	(17)
Algorithmic Level Design		185	(52)
General Algorithmic Model Development in the Behavioral Domain		186	(12)
Process Model Graph		187	(2)
Algorithmic Model of a Parallel to Serial Converter		189	(3)
Algorithmic Models with Timing		192	(3)
Checking Timing		195	(3)
Representation of System Interconnections		198	(6)
Comprehensive Algorithmic Modeling Example		199	(5)
Algorithmic Modeling of Systems		204	(33)
Multivalued Logic Systems		204	(8)
Comprehensive System Example		212	(10)
Time Multiplexing		222	(15)
Register Level Design		237	(24)
Transition from Algorithmic to Data Flow Descriptions		237	(4)
Transformation Example		238	(3)
Timing Analysis		241	(2)
Control Unit Design		243	(2)
Types of Control Units		243	(2)
Ultimate RISC Machine		245	(16)
Single URISC Instruction		246	(1)
URISC Architecture		246	(2)
URISC Control		248	(4)
URISC System		252	(1)
Design of the URISC at the Register Level		252	(2)
Microcoded Controller for the URISC Processor		254	(2)
Hardwired Controller for the URISC Processor		256	(5)
Gate Level and ASIC Library Modeling		261	(54)
Accurate Gate Level Modeling		261	(16)
Asymmetric Timing		262	(2)
Load Sensitive Delay Modeling		264	(5)
ASIC Cell Delay Modeling		269	(3)
Back Annotation of Delays		272	(3)
Vital: A Standard for the Generation of VHDL Models of Library Elements		275	(2)
Error Checking		277	(3)
Multivalued Logic for Gate Level Modeling		280	(12)
Additional Values for MOS Design		280	(1)
Generalized State/Strength Model		281	(5)
Interval Logic		286	(1)
Vantage System		286	(3)
Multivalued Gate-Level Models		289	(3)
Accurate Delay Modeling		292	(1)
Configuration Declarations for Gate Level Models		292	(7)
Default Configuration		296	(1)
Configurations and Component Libraries		297	(2)
Modeling Races and Hazards		299	(8)
Approaches to Delay Control		307	(8)
HDL-Based Design Techniques		315	(62)
Design of Combinational Logic Circuits		315	(14)
Combinational Logic Design at the Algorithmic Level		316	(7)
Design of Data Flow Models of Combinational Logic in the Behavioral Domain		323	(1)
Synthesis of Gate-Level Structural Domain Combinational Logic Circuits		324	(5)
Summary of Design Activity for Combinational Logic Circuits		329	(1)
Design of Sequential Logic Circuits		329	(16)
Moore of Mealy Decision		332	(1)
Construction of a State Table		333	(1)
Creating a State Diagram		333	(3)
Transition List Approach		336	(1)
Creating a VHDL Model for State Machines		337	(6)
Synthesis of VHDL State Machine Models		343	(2)
Design of Microprogrammed Control Units		345	(32)
Interface Between Controller and Device		345	(1)
Comparison of Hardwired and Microprogrammed Control Units		345	(3)
Basic Microprogrammed Control Unit		348	(1)
Algorithmic-Level Model of BMCU		349	(1)
Design of Microprogrammed Controllers for State Machines		350	(8)
Generalities and Limitations of Microprogrammed Control Units		358	(3)
Alternative Condition Select Methods		361	(3)
Alternative Branching Methods		364	(13)
ASICs and the ASIC Design Process		377	(52)
What is an ASIC?		377	(2)
ASIC Circuit Technology		379	(2)
CMOS Switches		380	(1)
Types of ASICs		381	(21)
PLDs		381	(1)
Field Programmable Gate Arrays		381	(11)
Gate Arrays		392	(2)
Standard Cells		394	(4)
Full Custom Chips		398	(1)
Relative Cost of ASICs and FPGAs		399	(3)
The ASIC Design Process		402	(16)
Standard Cell ASIC Synthesis		404	(11)
Post Synthesis Simulation		415	(3)
FPGA Synthesis		418	(11)
FPGA Example		419	(5)
Comparison with an ASIC Design		424	(5)
Modeling for Synthesis		429	(60)
Behavioral Model Development		429	(10)
Creation of the Initial Behavioral Model		430	(1)
Application-Domain Tools		431	(3)
Language-Domain Modeling		434	(3)
Modeling and Model Efficiency		437	(1)
Application-Domain vs. Language-Domain Modeling		438	(1)
The Semantics of Simulation and Synthesis		439	(16)
Delay in Models		444	(11)
Data Types		455	(1)
Modeling Sequential Behavior		455
Modeling Combinational Circuits for Synthesis		452	(13)
Synthesis of Arithmetic Circuits		457	(2)
Hierarchical Arithmetic Circuit: BCD to Binary Converter		459	(1)
Synthesis of Hierarchical Circuits		460	(5)
Inferred Latches and Don't Cares		465	(4)
Tristate Circuits		469	(2)
Shared Resources		471	(1)
Flattening and Structuring		472	(2)
Effect of Modeling Style On Circuit Complexity		474	(15)
Effect of Selection of Individual Construct		474	(2)
Effect of General Modeling Approach		476	(13)
Integration of VHDL into a Top-Down Design Methodology		489	(64)
Top-Down Design Methodology		489	(3)
Sobel Edge Detection Algorithm		492	(3)
System Requirements Level		495	(4)
Written specifications		495	(1)
Requirements Repository		495	(4)
System Definition Level		499	(24)
Executable Specification		499	(9)
Test Bench Development for Executable Specifications		508	(15)
Architecture Design		523	(7)
System Level Decomposition		523	(4)
Hierarchical Decomposition		527	(2)
Methodology for Development of Test Benches for a Hierarchical Structural Model		529	(1)
Detailed Design at the RTL Level		530	(15)
Register Transfer Level Design		531	(7)
Simulating structural Models Using Components with Different Data Types		538	(6)
Test Bench Development at the RTL		544	(1)
Detailed Design at the Gate Level		545	(8)
Gate-Level Design of Horizontal Filter		545	(1)
Optimization of Gate-Level Circuits		545	(2)
Gate-Level Testing		547	(1)
Methodology for Back Annotation		548	(5)
Synthesis Algorithms for Design Automation		553	(70)
Benefits of Algorithmic Synthesis		553	(1)
Algorithmic Synthesis Tasks		554	(11)
Compilation of VHDL Description into an Internal Format		556	(1)
Scheduling		556	(1)
Allocation		557	(1)
Interaction of Scheduling and Allocation		558	(4)
Gantt Charts and Utilization		562	(1)
Creating FSM VHDL from an Allocation Graph		563	(2)
Scheduling Techniques		565	(9)
Transformational Scheduling		566	(1)
Iterative/Constructive Scheduling		567	(1)
ASAP Scheduling		567	(1)
ALAP Scheduling		568	(2)
List Scheduling		570	(3)
Freedom-Directed Scheduling		573	(1)
Allocation Techniques		574	(26)
Greedy Allocation		574	(1)
Allocation by Exhaustive Search		575	(1)
Left Edge Algorithm		575	(2)
Assigning Functional Units and Interconnection Paths		577	(5)
Analysis of the Allocation Process		582	(2)
Nearly Minimal Cluster Partitioning Algorithm		584	(5)
Profit Directed Cluster Partitioning Algorithm (PDCPA)		589	(11)
State of the Art in High-Level Synthesis		600	(2)
Automated Synthesis of VHDL Constructs		602	(21)
Constructs that Involve Selection		602	(1)
Mapping case Statements to Multiplexers		602	(2)
Mapping if...then...else Statements to Multiplexers		604	(1)
Mapping Indexed Vector References to Multiplexers		605	(1)
Loop Constructs		605	(4)
Functions and Procedures		609	(14)
References		623	(10)
Index		633	(20)
About the Authors		653	(3)
About the CD		656

DR. JAMES R. ARMSTRONG and DR. F. GAIL GRAY are Professors of Electrical and Computer Engineering at Virginia Tech. Dr. Armstrong teaches graduate and undergraduate courses in computer architecture, HDLs, and logic design. He was a member of the original IEEE standardization committee; authored Chip Level Modeling With VHDL, and co-authored Structured Logic Design With VHDL, both from Prentice Hall. Dr. Gray teaches graduate and undergraduate courses in computer engineering, logic design, hardware description languages, coding theory, fault tolerant computing, testing, and microprocessor system design. His work has been published by IEEE Transactions on Computers; Journal of VLSI Signal Processing for Signal, Image, and Video Technology; Design Automation Conference; the VHDL International Users Forum; and many other leading journals and conferences.