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Session 1 - High-Level Design (1) |
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System-Level Application-Specific NoC Design for Network and Multimedia Applications |
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1 | (9) |
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Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements |
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10 | (10) |
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A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms |
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20 | (11) |
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An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture |
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31 | (12) |
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Session 2 - Low Power Design Techniques |
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Template Vertical Dictionary-Based Program Compression Scheme on the TTA |
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43 | (10) |
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Asynchronous Functional Coupling for Low Power Sensor Network Processors |
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53 | (11) |
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A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs |
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64 | (11) |
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Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports |
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75 | (11) |
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The Design and Implementation of a Power Efficient Embedded SRAM |
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86 | (11) |
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Session 3 - Low Power Analog Circuits |
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Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN |
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97 | (10) |
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Settling Time Minimization of Operational Amplifiers |
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107 | (10) |
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Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs |
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117 | (8) |
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Session 4 - Statistical Static Timing Analysis |
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Computation of Joint Timing Yield of Sequential Networks Considering Process Variations |
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125 | (13) |
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A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation |
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138 | (10) |
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A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits |
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148 | (12) |
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Session 5 - Power Modeling and Optimization |
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A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect |
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160 | (11) |
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Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components |
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171 | (10) |
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Logic Style Comparison for Ultra Low Power Operation in 65nm Technology |
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181 | (10) |
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Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation |
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191 | (10) |
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Session 6 - Low Power Routing Optimization |
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Clock Distribution Techniques for Low-EMI Design |
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201 | (10) |
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Crosstalk Waveform Modeling Using Wave Fitting |
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211 | (11) |
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Weakness Identification for Effective Repair of Power Distribution Network |
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222 | (10) |
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New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses |
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232 | (10) |
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On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects |
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242 | (13) |
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Session 7 - High Level Design (2) |
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Soft Error-Aware Power Optimization Using Gate Sizing |
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255 | (13) |
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Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices |
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268 | (10) |
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RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating |
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278 | (10) |
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Functional Verification of Low Power Designs at RTL |
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288 | (12) |
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XEEMU: An Improved XScale Power Simulator |
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300 | (10) |
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Session 8 - Security and Asynchronous Design |
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Low Power Elliptic Curve Cryptography |
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310 | (10) |
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Design and Test of Self-checking Asynchronous Control Circuit |
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320 | (10) |
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An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips |
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330 | (10) |
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Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA |
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340 | (12) |
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Session 9 - Low Power Applications |
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Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform |
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352 | (11) |
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The Energy Scalability of Wavelet-Based, Scalable Video Decoding |
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363 | (10) |
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Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption |
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373 | (11) |
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Poster 1 - Modeling and Optimization |
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Exploiting Input Variations for Energy Reduction |
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384 | (10) |
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A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates |
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394 | (10) |
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Static Power Consumption in CMOS Gates Using Independent Bodies |
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404 | (9) |
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Moderate Inversion: Highlights for Low Voltage Design |
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413 | (10) |
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On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems |
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423 | (10) |
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Semi Custom Design: A Case Study on SIMD Shufflers |
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433 | (10) |
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Nandhavel Sethubalasubramanian |
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Poster 2 - High Level Design |
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Optimization for Real-Time Systems with Non-convex Power Versus Speed Models |
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443 | (10) |
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Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS |
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453 | (10) |
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A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits |
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463 | (11) |
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Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates |
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474 | (11) |
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A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning |
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485 | (10) |
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Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems |
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495 | (10) |
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Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate |
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505 | (11) |
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Poster 3 - Low Power Techniques and Applications |
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A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations |
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516 | (10) |
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Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data |
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526 | (10) |
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Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply |
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536 | (10) |
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Low-Power Digital Filtering Based on the Logarithmic Number System |
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546 | (10) |
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A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling |
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556 | (10) |
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Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers |
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566 | (10) |
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Design and Industrialization Challenges of Memory Dominated SOCs |
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576 | (1) |
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Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies |
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577 | (1) |
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578 | (1) |
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Industrial Session - Design Challenges in Real-Life Projects |
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Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms |
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579 | (1) |
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System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters |
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580 | (1) |
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| Author Index |
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581 | |
